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Commit 960efc5e authored by Swapnil Jakhade's avatar Swapnil Jakhade Committed by Tom Rini
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phy: cadence: Sierra: Update single link PCIe register configuration



Add single link PCIe register configurations for no SSC and internal
SSC. Also, add missing PMA lane registers for external SSC.

Signed-off-by: default avatarSwapnil Jakhade <sjakhade@cadence.com>
Signed-off-by: default avatarAswath Govindraju <a-govindraju@ti.com>
parent f0cb8096
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