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Commit 8a647fc3 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Jagan Teki
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mmc: sunxi: Only update timing mode bit when enabling new timing mode



When enabling the new mmc timing mode, we inadvertently clear all the
remaining bits in the new timing mode register. The bits cleared
include a default phase delay on the output clock. The BSP kernel
states that the default values are supposed to be used. Clearing them
results in decreased performance or transfer errors on some boards.

Fixes: de9b1771 ("mmc: sunxi: Support new mode")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: default avatarJagan Teki <jagan@openedev.com>
parent ead3697d
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