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Commit 7a478c83 authored by Cem Tenruh's avatar Cem Tenruh Committed by Stefano Babic
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board: phytec: phycore_imx8mm: Update lpddr4_timing



Update RAM Timings for 2GB RAM based on DDR Controller Configuration
Spreadsheet revision 22. Including the update of the refresh
rate to workaround errata ERR050805.

Signed-off-by: default avatarCem Tenruh <c.tenruh@phytec.de>
parent ff1dd520
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