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Commit 79495766 authored by Ye Li's avatar Ye Li Committed by Stefano Babic
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spi: fsl_qspi: Fix DDR mode setting for latest iMX platforms



On latest iMX platforms like iMX7D/iMX6UL/iMX8MQ, the QSPI controller
is updated to have TDH field in FLSHCR register. According to reference
manual, this TDH must be set to 1 when DDR_EN is set. Otherwise, the TX
DDR delay logic won't be enabled.

Another issue in DDR mode is the MCR register will be overwritten in
every read/write/erase operation. This causes DDR_EN been cleared while
TDH=1, then no clk2x output for TX data shift and all operations will
fail.

Signed-off-by: default avatarYe Li <ye.li@nxp.com>
parent 4ee0ff12
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