net: dwc_eth_qos: restore support of not cache-aligned descriptor

Solve an issue with AXI_WIDTH_32 on a the 64 bytes cache line platform;
in this case the requested descriptor padding length should be 12 but the
associated parameter EQOS_DMA_CH0_CONTROL.DSL is limited to 3bits = 7.

As the DMA descriptor can't be correctly aligned with the cache line,
the maintenance of each descriptor can't be guaranteed by a simple cache
line operation: flush or invalid.

To avoid all the maintenance issues, these descriptors need to be allocated
in a NOT CACHEABLE memory by noncached_alloc() when
CONFIG_SYS_NONCACHED_MEMORY is enable.

This patch doesn't change the current behavior when the descriptors
can be cache-aligned with the field "Descriptor Skip Length" of
the DMA channel control register, when eqos->desc_pad = true.

Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>