mtd: spi-nor-core: Fix address width on flash chips > 16MB

If a flash chip has more than 16MB capacity but its BFPT reports
BFPT_DWORD1_ADDRESS_BYTES_3_OR_4, the spi-nor framework defaults to 3.

The check in spi_nor_scan() doesn't catch it because addr_width did get
set. This fixes that check.

Ported from Kernel commit 324f78dfb442b82365548b657ec4e6974c677502.

Signed-off-by: Pratyush Yadav <p.yadav@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>