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  1. Dec 01, 2020
  2. Nov 29, 2020
    • Jakub Kicinski's avatar
      Merge branch 'net-ipa-start-adding-ipa-v4-5-support' · e71d2b95
      Jakub Kicinski authored
      Alex Elder says:
      
      ====================
      net: ipa: start adding IPA v4.5 support
      
      This series starts updating the IPA code to support IPA hardware
      version 4.5.
      
      The first patch fixes a problem found while preparing these updates.
      Testing shows the code works with or without the change, and with
      the fix the code matches "downstream" Qualcomm code.
      
      The second patch updates the definitions for IPA register offsets
      and field masks to reflect the changes that come with IPA v4.5.  A
      few register updates have been deferred until later, because making
      use of them involves some nontrivial code updates.
      
      One type of change that IPA v4.5 brings is expanding the range of
      certain configuration values.  High-order bits are added in a few
      cases, and the third patch implements the code changes necessary to
      use those newly available bits.
      
      The fourth patch implements several fairly minor changes to the code
      required for IPA v4.5 support.
      
      The last two patches implement changes to the GSI registers used for
      IPA.  Almost none of the registers change, but the range of memory
      in which most of the GSI registers is located is shifted by a fixed
      amount.  The fifth patch updates the GSI register definitions, and
      the last patch implements the memory shift for IPA v4.5.
      ====================
      
      Link: https://lore.kernel.org/r/20201125204522.5884-1-elder@linaro.org
      
      
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      e71d2b95
    • Alex Elder's avatar
      net: ipa: adjust GSI register addresses · cdeee49f
      Alex Elder authored
      
      
      The offsets for almost all GSI registers we use have different
      offsets starting at IPA version 4.5.  Only two registers remain
      in their original location.
      
      In a way though, the new register locations are not *that*
      different.  The entire group of affected registers has simply
      been shifted down in memory by a fixed amount (0xd000).  So for
      example, the channel context 0 register that has a base offset of
      0x0001c000 for "older" hardware now has a base offset of 0x0000f000.
      
      This patch aims to add support for IPA v4.5 registers at their new
      offets in a way that minimizes the amount of code that needs to
      change.  It is not ideal, but it avoids the need to maintain
      a nearly complete set of additional register offset definitions.
      
      The approach takes advantage of the fact that when accessing GSI
      registers we do not access any of memory at lower end of the "gsi"
      memory range (with two exceptions already noted).  In particular,
      we do not access anything within the bottom 0xd000 bytes of the
      GSI memory range.
      
      For IPA version 4.5, after we map the GSI memory, we adjust the
      virtual memory pointer downward by the fixed amount (0xd000).
      That way, register accesses using the offsets defined by the
      existing GSI_REG_*() macros will resolve to the proper locations
      for IPA version 4.5.
      
      The two registers *not* affected by this offset are accessed only
      in gsi_irq_setup().  There, for IPA version 4.5, we undo the general
      register adjustment by adding the fixed amount back to the virtual
      address to access these registers.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      cdeee49f
    • Alex Elder's avatar
      net: ipa: update gsi registers for IPA v4.5 · b0b6f0dd
      Alex Elder authored
      
      
      Very few GSI register definitions change for IPA v4.5, however
      as a group their position in memory shifts a constant amount
      (handled by the next commit).
      
      Add definitions and update comments to the set of GSI registers to
      support changes that come with IPA v4.5.
      
      Update the logic in gsi_channel_program() to accommodate the new
      (expanded) PREFETCH_MODE field in the CH_C_QOS register.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      b0b6f0dd
    • Alex Elder's avatar
      net: ipa: add support to code for IPA v4.5 · 8bfc4e21
      Alex Elder authored
      
      
      Update the IPA code to make use of the updated IPA v4.5 register
      definitions.  Generally what this patch does is, if IPA v4.5
      hardware is in use:
        - Ensure new registers or fields in IPA v4.5 are updated where
          required
        - Ensure registers or fields not supported in IPA v4.5 are not
          examined when read, or are set to 0 when written
      It does this while preserving the existing functionality for IPA
      versions lower than v4.5.
      
      The values to program for QSB_MAX_READS and QSB_MAX_WRITES and the
      source and destination resource counts are updated to be correct for
      all versions through v4.5 as well.
      
      Note that IPA_RESOURCE_GROUP_SRC_MAX and IPA_RESOURCE_GROUP_DST_MAX
      already reflect that 5 is an acceptable number of resources (which
      IPA v4.5 implements).
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      8bfc4e21
    • Alex Elder's avatar
      net: ipa: add new most-significant bits to registers · 1af15c2a
      Alex Elder authored
      
      
      IPA v4.5 adds a few fields to the endpoint header and extended
      header configuration registers that represent new high-order bits
      for certain offsets and sizes.  Add code to incorporate these upper
      bits into the registers for IPA v4.5.
      
      This includes creating ipa_header_size_encoded(), which handles
      encoding the metadata offset field for use in the ENDP_INIT_HDR
      register in a way appropriate for the hardware version.  This and
      ipa_metadata_offset_encoded() ensure the mask argument passed to
      u32_encode_bits() is constant.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      1af15c2a
    • Alex Elder's avatar
      net: ipa: update IPA registers for IPA v4.5 · 5b6cd69e
      Alex Elder authored
      
      
      Update "ipa_reg.h" so that register definitions support IPA hardware
      version 4.5, in addition to versions 3.5.1 through v4.2.  Most of
      the register definitions are the same, but in some cases fields are
      added, changed, or eliminated.
      
      Updates for a few IPA v4.5 registers are more complex, and adding
      those definition will be deferred to separate patches.  This patch
      only updates the register offset and field definitions, and adds
      informational comments.
      
      The only code change avoids accessing the backward compatibility
      register for IPA version 4.5 in ipa_hardware_config().  Other IPA
      v4.5-specific code changes will come later.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      5b6cd69e
    • Alex Elder's avatar
      net: ipa: reverse logic on escape buffer use · 9f848198
      Alex Elder authored
      
      
      Starting with IPA v4.2 there is a GSI channel option to use an
      "escape buffer" instead of prefetch buffers.  This should be used
      for all channels *except* the AP command TX channel.  The logic
      that implements this has it backwards; fix this bug.
      
      Signed-off-by: default avatarAlex Elder <elder@linaro.org>
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      9f848198
    • Marcelo Ricardo Leitner's avatar
      net/sched: act_ct: enable stats for HW offloaded entries · 3567e233
      Marcelo Ricardo Leitner authored
      By setting NF_FLOWTABLE_COUNTER. Otherwise, the updates added by
      commit ef803b3c ("netfilter: flowtable: add counter support in HW
      offload") are not effective when using act_ct.
      
      While at it, now that we have the flag set, protect the call to
      nf_ct_acct_update() by commit beb97d3a
      
       ("net/sched: act_ct: update
      nf_conn_acct for act_ct SW offload in flowtable") with the check on
      NF_FLOWTABLE_COUNTER, as also done on other places.
      
      Note that this shouldn't impact performance as these stats are only
      enabled when net.netfilter.nf_conntrack_acct is enabled.
      
      Signed-off-by: default avatarMarcelo Ricardo Leitner <marcelo.leitner@gmail.com>
      Acked-by: default avatarwenxu <wenxu@ucloud.cn>
      Acked-by: default avatarPablo Neira Ayuso <pablo@netfilter.org>
      Link: https://lore.kernel.org/r/481a65741261fd81b0a0813e698af163477467ec.1606415787.git.marcelo.leitner@gmail.com
      
      
      Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
      3567e233
  3. Nov 28, 2020