gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler
Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins). The hwirq base for each sgpio bank should be multiples of 64 rather than multiples of 32. Signed-off-by:Steven Lee <steven_lee@aspeedtech.com> Signed-off-by:
Bartosz Golaszewski <brgl@bgdev.pl>
parent
c9e6606c
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