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Commit 9f5eb1bf authored by Bjorn Helgaas's avatar Bjorn Helgaas
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Merge branch 'pci/controller/rockchip'

- Remove writes to unused registers (Rick Wertenbroek)

- Write endpoint Device ID using correct register (Rick Wertenbroek)

- Assert PCI Configuration Enable bit after probe so endpoint responds
  instead of generating Request Retry Status messages (Rick Wertenbroek)

- Poll waiting for PHY PLLs to lock (Rick Wertenbroek)

- Update RK3399 example DT binding to be valid (Rick Wertenbroek)

- Use RK3399 PCIE_CLIENT_LEGACY_INT_CTRL to generate INTx instead of
  manually generating PCIe message (Rick Wertenbroek)

- Use multiple windows to avoid address translation conflicts (Rick
  Wertenbroek)

- Use u32 (not u16) when accessing 32-bit registers (Rick Wertenbroek)

- Hide MSI-X Capability, since RK3399 can't generate MSI-X (Rick
  Wertenbroek)

- Set endpoint controller required alignment to 256 (Damien Le Moal)

* pci/controller/rockchip:
  PCI: rockchip: Set address alignment for endpoint mode
  PCI: rockchip: Don't advertise MSI-X in PCIe capabilities
  PCI: rockchip: Use u32 variable to access 32-bit registers
  PCI: rockchip: Fix window mapping and address translation for endpoint
  PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core
  dt-bindings: PCI: Update the RK3399 example to a valid one
  PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked
  PCI: rockchip: Assert PCI Configuration Enable bit after probe
  PCI: rockchip: Write PCI Device ID to correct register
  PCI: rockchip: Remove writes to unused registers
parents 9cd5f2ce 7e6689b3
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