- Feb 25, 2019
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Aaro Koskinen authored
When running OMAP1 kernel on QEMU, MMC access is annoyingly noisy: MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! MMC: CTO of 0xff and 0xfe cannot be used! [ad inf.] Emulator warnings appear to be valid. The TI document SPRU680 [1] ("OMAP5910 Dual-Core Processor MultiMedia Card/Secure Data Memory Card (MMC/SD) Reference Guide") page 36 states that the maximum timeout is 253 cycles and "0xff and 0xfe cannot be used". Fix by using 0xfd as the maximum timeout. Tested using QEMU 2.5 (Siemens SX1 machine, OMAP310), and also checked on real hardware using Palm TE (OMAP310), Nokia 770 (OMAP1710) and Nokia N810 (OMAP2420) that MMC works as before. [1] http://www.ti.com/lit/ug/spru680/spru680.pdf Fixes: 730c9b7e ("[MMC] Add OMAP MMC host driver") Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
This patch adds HW Command Queue for supported Tegra SDMMC controllers. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Acked-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
Below are the supported DMA types in Host Control1 Register with Version 4 enable b'00 - SDMA b'01 - Not Used b'10 - ADMA2 b'11 - ADMA2 or ADMA3 ADMA3 uses Command Descriptor to issue an SD command. A multi-block data transfer is performed by using a pair of CMD descriptor and ADMA2 descriptor. ADMA3 performs multiple of multi-block data transfer by using Integrated Descriptor which is more suitable for Command Queuing to fetch both Command and Transfer descriptors. Host Capabilities register indicates the supports of ADMA3 DMA. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
Add supports-cqe optional property for MMC hosts. This property is used to identify the specific host controller supporting command queue. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ulf Hansson authored
The git tree isn't used to maintain SDHCI, but instead we use the common MMC git tree. Let's drop it to avoid confusion. Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com>
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Ulf Hansson authored
The eMMC CQHCI is the host controller interface, introduced in the eMMC spec v5.1. The code was originally developed as collaboration among several people, however none really stepped in to maintain it. Let's add Adrian Hunter (Intel), Ritesh Harjani and Asutosh Das as the maintainers, whom knows both the code and the spec. Cc: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Acked-by:
Ritesh Harjani <riteshh@codeaurora.org> Acked-by:
Asutosh Das <asutoshd@codeaurora.org>
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Nicolas Ferre authored
This patch adds support for 8-bit buswidth. Relevant SDCR value modified. Signed-off-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Reviewed-by:
Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Takeshi Saito authored
This fixes card initialization failure in high speed mode. If U-Boot uses SDR or HS200/400 mode before starting Linux and Linux DT does not enable SDR/HS200/HS400 mode, card initialization fails in high speed mode. It is necessary to initialize SCC registers during card initialization phase. HW reset function is registered only for a port with either of SDR/HS200/HS400 properties in device tree. If SDR/HS200/HS400 properties are not present in device tree, SCC registers will not be reset. In SoC that support SCC registers, HW reset function should be registered regardless of the configuration of device tree. Reproduction procedure: - Use U-Boot that support MMC HS200/400 mode. - Delete HS200/HS400 properties in device tree. (Delete mmc-hs200-1_8v and mmc-hs400-1_8v) - MMC port works high speed mode and all commands fail. Signed-off-by:
Takeshi Saito <takeshi.saito.xv@renesas.com> Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Cc: Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Cc: stable@vger.kernel.org Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Paul Cercueil authored
Drop the custom code to get the 'cd' and 'wp' GPIOs. The driver now calls mmc_of_parse() which will init these from devicetree or device properties. Also drop the custom code to get the 'power' GPIO. The MMC core provides us with the means to power the MMC card through an external regulator. Signed-off-by:
Paul Cercueil <paul@crapouillou.net> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ernest Zhang(WH) authored
O2 SD host controller only need set the quirk2 flag SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD when work on force 1.8v emmc mode but not normal mode Signed-off-by:
Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Mathieu Malaterre authored
There is a plan to build the kernel with -Wimplicit-fallthrough and these places in the code produced warnings (W=1). This commit removes the following warnings: drivers/mmc/host/jz4740_mmc.c:745:3: warning: this statement may fall through [-Wimplicit-fallthrough=] drivers/mmc/host/jz4740_mmc.c:779:3: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by:
Mathieu Malaterre <malat@debian.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wei Yongjun authored
In case of error, the function devm_kzalloc() returns NULL pointer not ERR_PTR(). The IS_ERR() test in the return value check should be replaced with NULL test. Fixes: fadac7488064 ("mmc: sdhci-esdhc-imx: add CMDQ support") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Mathieu Malaterre authored
There is a plan to build the kernel with -Wimplicit-fallthrough and this place in the code produced a warning (W=1). In this particular case rewrote the comment to start with the string "fall through", so as to match the regular expression expected by GCC. Truncate the comment slightly to fit the max line length of 80 characters. This commit remove the following warning: drivers/mmc/core/host.c:196:14: warning: this statement may fall through [-Wimplicit-fallthrough=] Signed-off-by:
Mathieu Malaterre <malat@debian.org> Acked-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
Program initial drive code offsets which will be used by auto calibration process. Program fixed drive strengths for SDMMC pads in pad control register when auto cal timeouts. Fixed settings are based on Pre-SI analysis of the pad design. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Sowjanya Komatineni authored
Add pinctrls for 3V3 and 1V8 pad drive strength configuration for Tegra210 sdmmc. Tegra210 sdmmc has pad configuration registers in pinmux register domain and handled thru pinctrl to pinmux device node. Tegra186 and Tegra194 has pad configuration register with in the SDMMC register domain itself and are handles thru drive strength properties in sdmmc device node. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
Currently, USDHC do not generate transfer complete interrupt when send a non-data-command with R1b response. But if want to support DCMD in CMDQ, need to change this, the DCMD IC logic require the USDHC to enable this function, otherwise DCMD will never get a CC(command complete) interrupt. This patch set ESDHC_VEND_SPEC2_EN_BUSY_IRQ and add DCMD support. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
Add CMDQ support for imx8qm/imx8qxp. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased on top of latest changes] Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
Change to use sdhci_set_timeout() to set the maximum timeout, so that the host can use it's own set_timeout() callback to set the maximum timeout if the host has. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
Add an new esdhc_soc_data for i.MX8QXP, and add HS400_ES mode support. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> [Ulf: Rebased on top of latest changes] Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
For some eMMC, after switch to HS400ES mode, it need to config the strobe dll target dealy even if the clock is 50MHZ or 25MHz, otherwise will meet CMD index/crc error when send CMD13 to check the switch status. [ 2.473915] IRQ status 0x000a8001 [ 2.473934] mmc2: mmc_select_hs400es failed, error -84 [ 2.473938] mmc2: error -84 whilst initialising MMC card Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Niklas Söderlund authored
When removing the driver make sure to undo the PM autosuspend configured when probing the host. Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Niklas Söderlund authored
Signed-off-by:
Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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wangbo authored
In sdio_bus_remove the variable is unneeded,remove it now. Signed-off-by:
wangbo <wang.bo116@zte.com.cn> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ernest Zhang(WH) authored
1. O2 Host Controller PLL lock status is not in compliance with CLOCK_CONTROL register bit 1 2. O2 Host Controller card detect function only work when PLL is enabled and locked Signed-off-by:
Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Ernest Zhang(WH) authored
Moving sdhci_o2 into sdhci-pci-o2micro.c Signed-off-by:
Ernest Zhang <ernest.zhang@bayhubtech.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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YueHaibing authored
Use DEFINE_DEBUGFS_ATTRIBUTE rather than DEFINE_SIMPLE_ATTRIBUTE for debugfs files. Semantic patch information: Rationale: DEFINE_SIMPLE_ATTRIBUTE + debugfs_create_file() imposes some significant overhead as compared to DEFINE_DEBUGFS_ATTRIBUTE + debugfs_create_file_unsafe(). Generated by: scripts/coccinelle/api/debugfs/debugfs_simple_attr.cocci Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Mike Maslenkin authored
Signed-off-by:
Mike Maslenkin <mike.maslenkin@gmail.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Stefan Wahren authored
We need to handle mmc_of_parse() errors during probe otherwise the MMC driver could start without proper initialization (e.g. power sequence). Fixes: 476bf3d6 ("mmc: sdhci-brcmstb: Add driver for Broadcom BRCMSTB SoCs") Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
When host set the host->tuning_delay, even the last tuning command need a delay, otherwise the first command after the tuning will meet issue. Take i.MX7D as an example, there will be the following log: mmc2: switch to high-speed from hs200 failed, err:-110 mmc2: error -110 whilst initialising MMC card Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
It's observed that i.MX uSDHC needed delay between tuning cycles for HS200 successful tuning. This patch is to set 1ms delay for that. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
i.MX6ULL has errata ERR010450, point out that due to SOC I/O timing limitation, for eMMC HS200 and SD/SDIO 3.0 SDR104, the clock rate can't exceed 150MHz. And for eMMC DDR52 and SD/SDIO DDR50 mode, the clock rate can't exceed 45MHz. This patch add this limit for imx6ull. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> [Ulf: Fixed comments and whitespace] Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
Add a imx6ull compatible string to be able to manage erratum ERR010450 on i.MX6ULL. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Reviewed-by:
Rob Herring <robh@kernel.org> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
Now tuning reset will be done when the timing is MMC_TIMING_LEGACY/ MMC_TIMING_MMC_HS/MMC_TIMING_SD_HS. But for timing MMC_TIMING_MMC_HS, we can not do tuning reset, otherwise HS400 timing is not right. Here is the process of init HS400, first finish tuning in HS200 mode, then switch to HS mode and 8 bit DDR mode, finally switch to HS400 mode. If we do tuning reset in HS mode, this will cause HS400 mode lost the tuning setting, which will cause CRC error. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Cc: stable@vger.kernel.org # v4.12+ Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Fixes: d9370424 ("mmc: sdhci-esdhc-imx: reset tuning circuit when power on mmc card") Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
DDR50 tuning is optinally defined in sd 3.0 spec. And i.MX uSDHC internally already uses a fixed optimized timing for DDR50, normally does not require tuning for DDR50 mode. This patch specify a new execute_tuning function for i.MX uSDHC, do not impact i.MX eSDHC. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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BOUGH CHEN authored
The bit ESDHC_STD_TUNING_EN may be configed by bootloader code if it choose to use standard tuning method. So on linux side, if choose to use manual tuning method, need to clear the bit ESDHC_STD_TUNING_EN, remove the impact of bootloader code. Signed-off-by:
Haibo Chen <haibo.chen@nxp.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Andrey Smirnov authored
Variant specific driver data doesn't change at run-time, so mark it as const to reflect that. Signed-off-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Acked-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Wei Yongjun authored
Fixes the following sparse warning: drivers/mmc/host/sdhci_am654.c:161:18: warning: symbol 'sdhci_am654_ops' was not declared. Should it be static? Fixes: aff88ff23512 ("mmc: sdhci_am654: Add Initial Support for AM654 SDHCI driver") Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/virt/kvm/kvmLinus Torvalds authored
Pull KVM fixes from Paolo Bonzini: "Bug fixes" * tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: KVM: MMU: record maximum physical address width in kvm_mmu_extended_role kvm: x86: Return LA57 feature based on hardware capability x86/kvm/mmu: fix switch between root and guest MMUs s390: vsie: Use effective CRYCBD.31 to check CRYCBD validity
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git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds authored
Pull networking fixes from David Miller: "Hopefully the last pull request for this release. Fingers crossed: 1) Only refcount ESP stats on full sockets, from Martin Willi. 2) Missing barriers in AF_UNIX, from Al Viro. 3) RCU protection fixes in ipv6 route code, from Paolo Abeni. 4) Avoid false positives in untrusted GSO validation, from Willem de Bruijn. 5) Forwarded mesh packets in mac80211 need more tailroom allocated, from Felix Fietkau. 6) Use operstate consistently for linkup in team driver, from George Wilkie. 7) ThunderX bug fixes from Vadim Lomovtsev. Mostly races between VF and PF code paths. 8) Purge ipv6 exceptions during netdevice removal, from Paolo Abeni. 9) nfp eBPF code gen fixes from Jiong Wang. 10) bnxt_en firmware timeout fix from Michael Chan. 11) Use after free in udp/udpv6 error handlers, from Paolo Abeni. 12) Fix a race in x25_bind triggerable by syzbot, from Eric Dumazet" * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (65 commits) net: phy: realtek: Dummy IRQ calls for RTL8366RB tcp: repaired skbs must init their tso_segs net/x25: fix a race in x25_bind() net: dsa: Remove documentation for port_fdb_prepare Revert "bridge: do not add port to router list when receives query with source 0.0.0.0" selftests: fib_tests: sleep after changing carrier. again. net: set static variable an initial value in atl2_probe() net: phy: marvell10g: Fix Multi-G advertisement to only advertise 10G bpf, doc: add bpf list as secondary entry to maintainers file udp: fix possible user after free in error handler udpv6: fix possible user after free in error handler fou6: fix proto error handler argument type udpv6: add the required annotation to mib type mdio_bus: Fix use-after-free on device_register fails net: Set rtm_table to RT_TABLE_COMPAT for ipv6 for tables > 255 bnxt_en: Wait longer for the firmware message response to complete. bnxt_en: Fix typo in firmware message timeout logic. nfp: bpf: fix ALU32 high bits clearance bug nfp: bpf: fix code-gen bug on BPF_ALU | BPF_XOR | BPF_K Documentation: networking: switchdev: Update port parent ID section ...
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