- Apr 03, 2019
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Martin Sperl authored
On long running tests with a mcp2517fd can controller it showed that on rare occations the data read shows corruptions for longer spi transfers. Example of a 22 byte transfer: expected (as captured on logic analyzer): FF FF 78 00 00 00 08 06 00 00 91 20 77 56 84 85 86 87 88 89 8a 8b read by the driver: FF FF 78 00 00 00 08 06 00 00 91 20 77 56 84 88 89 8a 00 00 8b 9b To fix this use BCM2835_AUX_SPI_STAT_RX_LVL to determine when we may read data from the fifo reliably without any corruption. Surprisingly the only values ever empirically read in BCM2835_AUX_SPI_STAT_RX_LVL are 0x00, 0x10, 0x20 and 0x30. So whenever the mask is not 0 we can read from the fifo in a safe manner. The patch has now been tested intensively and we are no longer able to reproduce the "RX" issue any longer. Fixes: 1ea29b39 ("spi: bcm2835aux: add bcm2835 auxiliary spi device...") Reported-by:
Hubert Denkmair <h.denkmair@intence.de> Signed-off-by:
Martin Sperl <kernel@martin.sperl.org> Acked-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Martin Sperl authored
This read of the fifo is a potential candidate for a race condition as the spi transfer is not necessarily finished and so can lead to an early read of the fifo that still misses data. So it has been removed. Fixes: 1ea29b39 ("spi: bcm2835aux: add bcm2835 auxiliary spi device...") Suggested-by:
Hubert Denkmair <h.denkmair@intence.de> Signed-off-by:
Martin Sperl <kernel@martin.sperl.org> Acked-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Martin Sperl authored
Sharing more code between polling and interrupt-driven mode. Signed-off-by:
Martin Sperl <kernel@martin.sperl.org> Acked-by:
Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Naga Sureshkumar Relli authored
Export spi_mem_default_supports_op(), so that controller drivers can use this. spi-mem driver already exports this using EXPORT_SYMBOL, but not declared it in spi-mem.h. This patch declares spi_mem_default_supports_op() in spi-mem.h and also removes the static from the function prototype. Signed-off-by:
Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Geert Uytterhoeven authored
Improve maintainability by converting the register bit, bitmask, and bitfield definitions from hexadecimal constants to constructs using BIT(), GENMASK(), or "val << shift". Suggested-by:
Simon Horman <horms+renesas@verge.net.au> Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Apr 02, 2019
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Rasmus Villemoes authored
Taking one interrupt for every byte is rather slow. Since the controller is perfectly capable of transmitting 32 bits at a time, change t->bits_per-word to 32 when the length is divisible by 4 and large enough that the reduced number of interrupts easily compensates for the one or two extra fsl_spi_setup_transfer() calls this causes. Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Rasmus Villemoes authored
Commit c9bfcb31 (spi_mpc83xx: much improved driver) introduced logic to ensure bits_per_word and speed_hz stay the same for a series of spi_transfers with CS active, arguing that The current driver may cause glitches on SPI CLK line since one must disable the SPI controller before changing any HW settings. This sounds quite reasonable. So this is a quite naive attempt at relaxing this sanity checking to only ensure that speed_hz is constant - in the faint hope that if we do not causes changes to the clock-related fields of the SPMODE register (DIV16 and PM), those glitches won't appear. The purpose of this change is to allow automatically optimizing large transfers to use 32 bits-per-word; taking one interrupt for every byte is extremely slow. Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Jarkko Nikula authored
Use SPI device pointer in the remaining two error and warning prints in pxa2xx_spi_transfer_one() instead of platform device of the controller It make prints in the function uniform and more useful especially the error print here as it can reveal the driver that has mapped the DMA itself and attempts to transfer more than the maximum supported DMA transfer length. Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Jarkko Nikula authored
Pointer to a SPI device is passed to pxa2xx_spi_transfer_one() so there is no need to access it through the current SPI message pointer. Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Apr 01, 2019
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Sowjanya Komatineni authored
Tegra SPI controller supports lsb first mode. Default is MSB bit first and on selection of SPI_LSB_FIRST through SPI mode transmission happens with LSB bit first. This patch adds SPI_LSB_FIRST flag to mode_bits and also configures it on request. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Sowjanya Komatineni authored
Fixes: Use packed mode for 32 bits per word transfers to increase performance as each packet is a full 32-bit word. Signed-off-by:
Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Rasmus Villemoes authored
The comment says that we should not allow changes (to bits_per_word/speed_hz) while CS is active, and indeed the code below does fsl_spi_setup_transfer() when the ->cs_change of the previous spi_transfer was set (and for the very first transfer). So the sanity checking is a bit too strict - we can change it to follow the same logic as is used by the actual transfer loop. Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Rasmus Villemoes authored
__spi_validate() in the generic SPI code sets ->speed_hz and ->bits_per_word to non-zero values, so this condition is always true. Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Mar 26, 2019
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Ludovic Barre authored
This patch adds the dma support for the stm32-qspi hardware. The memory buffer constraints (lowmem, vmalloc, kmap) are taken into account by framework. In read mode, the memory map is preferred vs dma (due to better throughput). If the dma transfer fails the buffer is sent by polling. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Ludovic Barre authored
This patch adds spi_master_put in release function to drop the controller's refcount. Signed-off-by:
Ludovic Barre <ludovic.barre@st.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Mar 25, 2019
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Stefan Roese authored
This patch moves the MT7621 SPI driver, which is used on some Ralink / MediaTek MT76xx MIPS SoC's, out of the staging directory. No changes to the source code are done in this patch. This driver version was tested successfully on an MT7688 based platform with an SPI NOR on CS0 and an SPI NAND on CS1 without any issues (so far). This patch also documents the devicetree bindings for the MT7621 SPI device driver. Signed-off-by:
Stefan Roese <sr@denx.de> Cc: Rob Herring <robh@kernel.org> Cc: Mark Brown <broonie@kernel.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: NeilBrown <neil@brown.name> Cc: Sankalp Negi <sankalpnegi2310@gmail.com> Cc: Chuanhong Guo <gch981213@gmail.com> Cc: John Crispin <john@phrozen.org> Cc: Armando Miraglia <arma2ff0@gmail.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Axel Lin authored
This checking is already done in __spi_validate_bits_per_word(). Signed-off-by:
Axel Lin <axel.lin@ingics.com> Acked-by:
Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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YueHaibing authored
Fix sparse warning: drivers/spi/atmel-quadspi.c:369:12: warning: symbol 'atmel_qspi_get_name' was not declared. Should it be static? Signed-off-by:
YueHaibing <yuehaibing@huawei.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Mar 21, 2019
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Arnd Bergmann authored
The newly added tracepoints in the spi-mxs driver cause a link error when the driver is a loadable module: ERROR: "__tracepoint_spi_transfer_stop" [drivers/spi/spi-mxs.ko] undefined! ERROR: "__tracepoint_spi_transfer_start" [drivers/spi/spi-mxs.ko] undefined! I'm not quite sure where to put the export statements, but directly after the inclusion of the header seems as good as any other place. Fixes: f3fdea3a ("spi: mxs: add tracing to custom .transfer_one_message callback") Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Andy Shevchenko authored
It's useful during debug to see what DMA burst size is. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Andy Shevchenko authored
Some masters may have different DMA burst size than hard coded default. In such case respect the value given by DMA burst size provided via platform data. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Reviewed-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Phil Edworthy authored
The Synopsys SSI Controller has an interface clock, but most SoCs hide this away. However, on some SoCs you need to explicitly enable the interface clock in order to access the registers. Therefore, add support for an optional interface clock. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Gareth Williams authored
Add documentation to the Synopsys SPI dt-bindings to support an optional interface clock that may be used for register access. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Phil Edworthy authored
The Synopsys SSI driver uses a mandatory clock that is not documented, so detail it in the device tree bindings. Also correct the spelling of "pins" in the "Optional Properties" section for the driver. Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
Gareth Williams <gareth.williams.jx@renesas.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Wolfram Sang authored
We should get 'driver_data' from 'struct device' directly. Going via platform_device is an unneeded step back and forth. Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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kbuild test robot authored
Fixes: 2e541b64 ("spi: spi-mem: stm32-qspi: add suspend/resume support") Signed-off-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Mar 19, 2019
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Mark Brown authored
Linux 5.1-rc1
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Andy Shevchenko authored
There is nothing in the driver which requires OF specific header to be included. Remove it for good. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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kbuild test robot authored
Fixes: 944c01a8 ("spi: lpspi: enable runtime pm for lpspi") Signed-off-by:
kbuild test robot <lkp@intel.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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- Mar 18, 2019
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Rasmus Villemoes authored
The MPC8309 has a dedicated signal, SPISEL_BOOT, usually used as chip select for the flash device from which the bootloader is loaded. It is not an ordinary gpio, but is simply controlled via the SPI_CS register in the system configuration. To allow accessing such a spi slave, we need to teach fsl_spi_cs_control() how to control the SPISEL_BOOT signal. To distinguish the gpio-controlled slaves, continue to have those use chip_select values of 0..ngpios-1, and use chip_select == ngpios for the boot flash. I'm not too happy with all the ifdeffery, but it seems to be necessary for guarding the sysdev/fsl_soc.h and use of get_immrbase() (spi-fsl-lib.c already contains similar ifdeffery). Googling suggests that the MPC8306 is similar, with the SPI_CS register at the same offset. Signed-off-by:
Rasmus Villemoes <rasmus.villemoes@prevas.dk> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Jan Kundrát authored
Signed-off-by:
Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Jan Kundrát authored
Commit b7bb367a added support for inserting delays in between individual words within a single SPI transaction. This makes it accessible from userspace. WARNING: This delay is silently ignored unless the SPI controller implements extra support for it. This is similar to how the in-kernel users handle the other existing property, spi_transfer->word_delay. Signed-off-by:
Jan Kundrát <jan.kundrat@cesnet.cz> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
Delete the extra space. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
The spi_transfer *t will be used in one transfer whatever. If t is NULL, there has no need to try sending data, so add an error return here. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Acked-by:
Fugang Duan <Fugang.duan@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
Add dma mode support for LPSPI. Any frame longer than half txfifosize will be sent by dma mode. For now, there are some limits: 1. The maximum transfer speed in master mode depends on the slave device, at least 40MHz(tested by spi-nor on 8qm-lpddr4-arm2 base board); 2. The maximum transfer speed in slave mode is 15MHz(imx7ulp), 22MHz(8qm/qxp). In order to reach the maximum speed which is mentioned in datasheet, the load of connect wires between master and slave should be less than 15pF. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Acked-by:
Fugang Duan <Fugang.duan@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
Use the default implementation of transfer_one_msg/chipselect/setup functions in spi core to implement cs-gpio control. Use fsl_lpspi_prepare_message to init the cs_gpio pin. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Acked-by:
Fugang Duan <Fugang.duan@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
Add a error info when set a speed which greater than half of per-clk of spi module. The minimum SCK period is 2 cycles(CCR[SCKDIV]). So the maximum transfer speed is half of spi per-clk. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Han Xu authored
Enable the runtime power management for lpspi module. Do some adaptation work from kernel 4.9 to 4.14. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Han Xu <han.xu@nxp.com> Reviewed-by:
Frank Li <frank.li@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
Add introductions of clocks and clock-names strings. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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Clark Wang authored
Add both ipg and per clock for lpspi to support i.MX8QM/QXP boards. Signed-off-by:
Clark Wang <xiaoning.wang@nxp.com> Signed-off-by:
Mark Brown <broonie@kernel.org>
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