spi: cadence-quadspi: fix write completion support
Some versions of the Cadence QSPI controller does not have the write completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is not configured. Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register. Fixes: 9cb2ff11 ("spi: cadence-quadspi: Disable Auto-HW polling) Signed-off-by:Dinh Nguyen <dinguyen@kernel.org> Reviewed-by:
Pratyush Yadav <p.yadav@ti.com> Link: https://lore.kernel.org/r/20211108200854.3616121-1-dinguyen@kernel.org Signed-off-by:
Mark Brown <broonie@kernel.org>
parent
28b5eaf9