arm64: dts: Add support for NXP LS1028A SoC
LS1028A contains two ARM v8 CortexA72 processor cores with 32 KB L1-D cache and 48 KB L1-I cache Features summary Two 32-bit / 64-bit ARM v8 Cortex-A72 CPUs - Arranged as single clusters of two cores sharing a 1 MB L2 cache - Speed Up to 1.3 GHz - Support for cluster power-gating. Cache coherent interconnect (CCI-400) - Hardware-managed data coherency - Up to 400 MHz 32-bit DDR4 SDRAM memory controller with ECC Two PCIe 3.0 controllers One serial ATA (SATA 3.0) controller Two high-speed USB 3.0 controllers with integrated PHY Following levels of DTSI/DTS files have been created for the LS1028A SoC family: - fsl-ls1028a.dtsi: DTS-Include file for NXP LS1028A SoC. - fsl-ls1028a-qds.dts: DTS file for NXP LS1028A QDS board. - fsl-ls1028a-rdb.dts: DTS file for NXP LS1028A RDB board Signed-off-by:Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by:
Rai Harninder <harninder.rai@nxp.com> Signed-off-by:
Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Acked-by:
Li Yang <leoyang.li@nxp.com> Signed-off-by:
Shawn Guo <shawnguo@kernel.org>
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