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Commit 52ae30f5 authored by Vignesh Raghavendra's avatar Vignesh Raghavendra Committed by Nishanth Menon
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arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent

Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC.  Add missing dma-coherent property to main_navss node.

Also add dma-ranges to be consistent with mcu_navss node
and with AM65/J721e main_navss and mcu_navss nodes.

Fixes: d361ed88

 ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: default avatarVignesh Raghavendra <vigneshr@ti.com>
Reviewed-by: default avatarPeter Ujfalusi <peter.ujfalusi@gmail.com>
Signed-off-by: default avatarNishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210510180601.19458-1-vigneshr@ti.com
parent df61cd93
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