mfd: Set asic3 DS1WM clock_rate
The mfd/asic3 driver does not set the ds1wm_driver_data clock_rate field before passing the structure to the DS1WM w1 busmaster driver. This was not noticed before commit 26a6afb9 , because ds1wm_find_divisor() unintentionally returned the correct divisor when a zero clock_rate was passed in. However after that commit DS1WM fails a zero clock_rate: ds1wm ds1wm: no suitable divisor for 0Hz clock This patch sets the ds1wm_driver_data clock_rate field. Signed-off-by:Paul Parsons <lost.distance@yahoo.com> Acked-by:
Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by:
Samuel Ortiz <sameo@linux.intel.com>
parent
e1277f45
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