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Commit cfd50dfb authored by Suman Anna's avatar Suman Anna Committed by Tom Rini
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clk: ti: k3: Update driver to account for divider flags



The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in
turn serve as inputs to other HSDIV output clocks. These clocks use
the actual value to compute the divider clock rate, and need to be
registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk
driver and data lacks the infrastructure to pass in divider flags.
Update the driver and data to account for these divider flags.

Signed-off-by: default avatarSuman Anna <s-anna@ti.com>
Signed-off-by: default avatarDave Gerlach <d-gerlach@ti.com>
parent d3c56e2a
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