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Commit a942c0c3 authored by Christian Marangi's avatar Christian Marangi Committed by Tom Rini
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clk: mediatek: mt7622: add missing clock MUX1_SEL 



Add missing infra clock MUX1_SEL needed for CPU clock. This is needed to
match the upstream clk ID order in preparation for OF_UPSTREAM.

Signed-off-by: default avatarChristian Marangi <ansuelsmth@gmail.com>
parent 6dfa9912
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