doc: board: ti: am62x_sk: Add A53 SPL DDR layout
To understand usage of DDR in A53 SPL stage, add a table showing region and space used by major components of SPL. Signed-off-by:Nikhil M Jain <n-jain1@ti.com> Reviewed-by:
Tom Rini <trini@konsulko.com>
Loading
Please register or sign in to comment