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Commit 9d8f814b authored by Dinesh Maniyam's avatar Dinesh Maniyam Committed by Tien Fong Chee
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clk: altera: n5x: Fix MEMCLKMGR_EXTCNTRST_C0CNTRST to bit(0)



MEMCLKMGR_EXTCNTRST_C0CNTRST register defined as BIT[0] in documentation
but it is wrongly defined as BIT[7] in u-boot code. This register is used
to hold associated pingpong counter in reset
while PLL and 5:1 mux configuration is changed.

Signed-off-by: default avatarDinesh Maniyam <dinesh.maniyam@intel.com>
Reviewed-by: default avatarTien Fong Chee <tien.fong.chee@intel.com>
parent 158d648d
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