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Commit 81b56a55 authored by Nikita Shubin's avatar Nikita Shubin Committed by Leo Yu-Chi Liang
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riscv: cpu: check U-Mode before counteren write



The Priv ISA states:
"In systems without U-mode, the mcounteren register should
not exist."

Check U-Mode is present in MISA before writing to counteren, otherwise
we endup with Illegal Instruction exception on systems without U-Mode.

Also make checking MISA default for M-Mode.

Signed-off-by: default avatarNikita Shubin <n.shubin@yadro.com>
Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
parent 73a3f513
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