riscv: cpu: check U-Mode before counteren write
The Priv ISA states: "In systems without U-mode, the mcounteren register should not exist." Check U-Mode is present in MISA before writing to counteren, otherwise we endup with Illegal Instruction exception on systems without U-Mode. Also make checking MISA default for M-Mode. Signed-off-by:Nikita Shubin <n.shubin@yadro.com> Reviewed-by:
Leo Yu-Chi Liang <ycliang@andestech.com>
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