cache: l2x0: Fix missing write to Auxiliary Control Register

In commit f62782fb ("cache: l2x0: Fix write to incorrect shared-override
bit") we removed writel to regs->pl310_aux_ctrl by accident.  This
commit restores it back.

Fixes: f62782fb ("cache: l2x0: Fix write to incorrect shared-override bit")
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>