riscv: semihosting: correct alignment
Commit 7400d34b ("riscv: semihosting: replace inline assembly with assembly file") reduced the alignment of function smh_trap(). As described in the "RISC-V Semihosting" specification [1] the ssli, ebreak, and srai statements must all reside in the same memory page. [1] RISC-V Semihosting, Version 0.4, 12th June 2024 https://github.com/riscv-non-isa/riscv-semihosting Fixes: 7400d34b ("riscv: semihosting: replace inline assembly with assembly file") Signed-off-by:Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by:
Leo Yu-Chi Liang <ycliang@andestech.com>
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