board: freescale: p1_p2_rdb_pc: Remove I-flag from second L2 SRAM mapping
U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with locked lines. P2020 reference manual about L2 memory-mapping mode says: Accesses to memory-mapped SRAM are cacheable only in the corresponding e500 L1 caches. So there is no need to set Caching-Inhibit I-bit for second part of initial L2 SRAM mapping in TLB entry. Remove it. First part of initial L2 SRAM mapping already does not have I-bit set. For more details see also: https://lore.kernel.org/u-boot/20220508150844.qqxg452rs4wtf5bs@pali/ Signed-off-by:Pali Rohár <pali@kernel.org>
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