riscv: Fix build against binutils 2.38
The following description is copied from the equivalent patch for the Linux Kernel proposed by Aurelien Jarno: >From version 2.38, binutils default to ISA spec version 20191213. This means that the csr read/write (csrr*/csrw*) instructions and fence.i instruction has separated from the `I` extension, become two standalone extensions: Zicsr and Zifencei. As the kernel uses those instruction, this causes the following build failure: arch/riscv/cpu/mtrap.S: Assembler messages: arch/riscv/cpu/mtrap.S:65: Error: unrecognized opcode `csrr a0,scause' arch/riscv/cpu/mtrap.S:66: Error: unrecognized opcode `csrr a1,sepc' arch/riscv/cpu/mtrap.S:67: Error: unrecognized opcode `csrr a2,stval' arch/riscv/cpu/mtrap.S:70: Error: unrecognized opcode `csrw sepc,a0' Signed-off-by:Alexandre Ghiti <alexandre.ghiti@canonical.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Tested-by:
Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Tested-by:
Heiko Stuebner <heiko@sntech.de> Tested-by:
Christian Stewart <christian@paral.in> Reviewed-by:
Rick Chen <rick@andestech.com>