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Commit 005f9627 authored by Xingyu Wu's avatar Xingyu Wu Committed by Leo Yu-Chi Liang
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riscv: dts: jh7110: Add PLL clock controller node



Add child node about PLL clock controller in sys_syscon node.

Signed-off-by: default avatarXingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: default avatarHal Feng <hal.feng@starfivetech.com>
Reviewed-by: default avatarTorsten Duwe <duwe@suse.de>
Reviewed-by: default avatarLeo Yu-Chi Liang <ycliang@andestech.com>
parent 2d7a5787
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