Commit ff9f1683 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/dwc' 

- Support multiple ATU memory regions (Rob Herring)

- Warn if non-prefetchable memory aperture is > 32-bit (Vidya Sagar)

- Allow programming ATU for >4GB memory (Vidya Sagar)

- Move ATU offset out of driver match data (Rob Herring)

- Move "dbi", "dbi2", and "addr_space" resource setup to common code (Rob
  Herring)

- Remove unneeded function wrappers (Rob Herring)

- Ensure all outbound ATU windows are reset to reduce dependencies on
  bootloader (Rob Herring)

- Use the default MSI irq_chip for dra7xx (Rob Herring)

- Drop the .set_num_vectors() host op (Rob Herring)

- Move MSI interrupt setup into DWC common code (Rob Herring)

- Rework and simplify DWC MSI initialization (Rob Herring)

- Move link handling to DWC common code (Rob Herring)

- Move dw_pcie_msi_init() calls to DWC common code (Rob Herring)

- Move dw_pcie_setup_rc() calls to DWC common code (Rob Herring)

- Remove unnecessary wrappers around dw_pcie_host_init() (Rob Herring)

- Revert "keystone: Drop duplicated 'num-viewport'" to prepare for
  detecting number of iATU regions without help from DT (Rob Herring)

- Move inbound and outbound windows to common struct (Rob Herring)

- Detect number of DWC iATU windows from device registers (Rob Herring)

- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)

- Add samsung,exynos-pcie and samsung,exynos-pcie-phy bindings for
  Exynos5433 variant (Marek Szyprowski)

- Rework phy-exynos-pcie driver to support Exynos5433 PCIe PHY (Jaehoon
  Chung)

- Rework pci-exynos.c to support Exynos5433 PCIe host (Jaehoon Chung)

- Move tegra "dbi" accesses to post common DWC initialization (Vidya Sagar)

- Read tegra dbi" base address in application logic (Vidya Sagar)

- Fix tegra ASPM-L1SS advertisement disable code (Vidya Sagar)

- Set Tegra194 DesignWare IP version to 0x490A (Vidya Sagar)

- Continue tegra unconfig sequence even if parts fail (Vidya Sagar)

- Check return value of tegra_pcie_init_controller() (Vidya Sagar)

- Disable tegra LTSSM during L2 entry (Vidya Sagar)

- Add SM8250 SoC PCIe DT bindings and support (Manivannan Sadhasivam)

- Add SM8250 BDF to SID mapping (Manivannan Sadhasivam)

- Set 32-bit DMA mask for DWC MSI target address allocation (Vidya Sagar)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
  PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
  PCI: qcom: Add SM8250 SoC support
  dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
  PCI: tegra: Disable LTSSM during L2 entry
  PCI: tegra: Check return value of tegra_pcie_init_controller()
  PCI: tegra: Continue unconfig sequence even if parts fail
  PCI: tegra: Set DesignWare IP version
  PCI: tegra: Fix ASPM-L1SS advertisement disable code
  PCI: tegra: Read "dbi" base address to program in application logic
  PCI: tegra: Move "dbi" accesses to post common DWC initialization
  PCI: dwc: exynos: Rework the driver to support Exynos5433 variant
  phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
  dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
  dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
  dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
  PCI: dwc: Detect number of iATU windows
  PCI: dwc: Move inbound and outbound windows to common struct
  Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'"
  PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init()
  PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
  PCI: dwc: Move dw_pcie_msi_init() into core
  PCI: dwc: Move link handling into common code
  PCI: dwc: Rework MSI initialization
  PCI: dwc: Move MSI interrupt setup into DWC common code
  PCI: dwc: Drop the .set_num_vectors() host op
  PCI: dwc/dra7xx: Use the common MSI irq_chip
  PCI: dwc: Ensure all outbound ATU windows are reset
  PCI: dwc/intel-gw: Remove some unneeded function wrappers
  PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
  PCI: dwc/intel-gw: Move ATU offset out of driver match data
  PCI: dwc: Add support to program ATU for >4GB memory
  PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
  PCI: dwc: Support multiple ATU memory regions
parents ee4871d0 660c4865

Documentation/devicetree/bindings/pci/qcom,pcie.txt

+4 −2
Original line number Diff line number Diff line
@@ -13,6 +13,7 @@ 
			- "qcom,pcie-ipq8074" for ipq8074

			- "qcom,pcie-qcs404" for qcs404

			- "qcom,pcie-sdm845" for sdm845

			- "qcom,pcie-sm8250" for sm8250



- reg:

	Usage: required
@@ -27,6 +28,7 @@ 
			- "dbi"	   DesignWare PCIe registers

			- "elbi"   External local bus interface registers

			- "config" PCIe configuration space

			- "atu"    ATU address space (optional)



- device_type:

	Usage: required
@@ -131,7 +133,7 @@ 
			- "slave_bus"	AXI Slave clock



-clock-names:

	Usage: required for sdm845

	Usage: required for sdm845 and sm8250

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "aux"		Auxiliary clock
@@ -206,7 +208,7 @@ 
			- "ahb"			AHB reset



- reset-names:

	Usage: required for sdm845

	Usage: required for sdm845 and sm8250

	Value type: <stringlist>

	Definition: Should contain the following entries

			- "pci"			PCIe core reset

Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml

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+119 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/pci/samsung,exynos-pcie.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung SoC series PCIe Host Controller Device Tree Bindings



maintainers:

  - Marek Szyprowski <m.szyprowski@samsung.com>

  - Jaehoon Chung <jh80.chung@samsung.com>



description: |+

  Exynos5433 SoC PCIe host controller is based on the Synopsys DesignWare

  PCIe IP and thus inherits all the common properties defined in

  designware-pcie.txt.



allOf:

  - $ref: /schemas/pci/pci-bus.yaml#



properties:

  compatible:

    const: samsung,exynos5433-pcie



  reg:

    items:

      - description: Data Bus Interface (DBI) registers.

      - description: External Local Bus interface (ELBI) registers.

      - description: PCIe configuration space region.



  reg-names:

    items:

      - const: dbi

      - const: elbi

      - const: config



  interrupts:

    maxItems: 1



  clocks:

    items:

      - description: PCIe bridge clock

      - description: PCIe bus clock



  clock-names:

    items:

      - const: pcie

      - const: pcie_bus



  phys:

    maxItems: 1



  vdd10-supply:

    description:

      Phandle to a regulator that provides 1.0V power to the PCIe block.



  vdd18-supply:

    description:

      Phandle to a regulator that provides 1.8V power to the PCIe block.



  num-lanes:

    const: 1



  num-viewport:

    const: 3



required:

  - reg

  - reg-names

  - interrupts

  - "#address-cells"

  - "#size-cells"

  - "#interrupt-cells"

  - interrupt-map

  - interrupt-map-mask

  - ranges

  - bus-range

  - device_type

  - num-lanes

  - num-viewport

  - clocks

  - clock-names

  - phys

  - vdd10-supply

  - vdd18-supply



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/clock/exynos5433.h>



    pcie: pcie@15700000 {

        compatible = "samsung,exynos5433-pcie";

        reg = <0x15700000 0x1000>, <0x156b0000 0x1000>, <0x0c000000 0x1000>;

        reg-names = "dbi", "elbi", "config";

        #address-cells = <3>;

        #size-cells = <2>;

        #interrupt-cells = <1>;

        device_type = "pci";

        interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&cmu_fsys CLK_PCIE>, <&cmu_fsys CLK_PCLK_PCIE_PHY>;

        clock-names = "pcie", "pcie_bus";

        phys = <&pcie_phy>;

        pinctrl-0 = <&pcie_bus &pcie_wlanen>;

        pinctrl-names = "default";

        num-lanes = <1>;

        num-viewport = <3>;

        bus-range = <0x00 0xff>;

        ranges = <0x81000000 0 0	  0x0c001000 0 0x00010000>,

                 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;

        vdd10-supply = <&ldo6_reg>;

        vdd18-supply = <&ldo7_reg>;

        interrupt-map-mask = <0 0 0 0>;

        interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;

    };

...

Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt

deleted100644 → 0
+0 −58
Original line number Diff line number Diff line 
* Samsung Exynos 5440 PCIe interface



This PCIe host controller is based on the Synopsys DesignWare PCIe IP

and thus inherits all the common properties defined in designware-pcie.txt.



Required properties:

- compatible: "samsung,exynos5440-pcie"

- reg: base addresses and lengths of the PCIe controller,

- reg-names : First name should be set to "elbi".

	And use the "config" instead of getting the configuration address space

	from "ranges".

	NOTE: When using the "config" property, reg-names must be set.

- interrupts: A list of interrupt outputs for level interrupt,

	pulse interrupt, special interrupt.

- phys: From PHY binding. Phandle for the generic PHY.

	Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt



For other common properties, refer to

	Documentation/devicetree/bindings/pci/designware-pcie.txt



Example:



SoC-specific DT Entry (with using PHY framework):



	pcie_phy0: pcie-phy@270000 {

		...

		reg = <0x270000 0x1000>, <0x271000 0x40>;

		reg-names = "phy", "block";

		...

	};



	pcie@290000 {

		compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";

		reg = <0x290000 0x1000>, <0x40000000 0x1000>;

		reg-names = "elbi", "config";

		clocks = <&clock 28>, <&clock 27>;

		clock-names = "pcie", "pcie_bus";

		#address-cells = <3>;

		#size-cells = <2>;

		device_type = "pci";

		phys = <&pcie_phy0>;

		ranges = <0x81000000 0 0	  0x60001000 0 0x00010000

			  0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;

		#interrupt-cells = <1>;

		interrupt-map-mask = <0 0 0 0>;

		interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;

		num-lanes = <4>;

	};



Board-specific DT Entry:



	pcie@290000 {

		reset-gpio = <&pin_ctrl 5 0>;

	};



	pcie@2a0000 {

		reset-gpio = <&pin_ctrl 22 0>;

	};

Documentation/devicetree/bindings/phy/samsung,exynos-pcie-phy.yaml

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+51 −0
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung SoC series PCIe PHY Device Tree Bindings



maintainers:

  - Marek Szyprowski <m.szyprowski@samsung.com>

  - Jaehoon Chung <jh80.chung@samsung.com>



properties:

  "#phy-cells":

    const: 0



  compatible:

    const: samsung,exynos5433-pcie-phy



  reg:

    maxItems: 1



  samsung,pmu-syscon:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: phandle for PMU system controller interface, used to

                 control PMU registers bits for PCIe PHY



  samsung,fsys-sysreg:

    $ref: '/schemas/types.yaml#/definitions/phandle'

    description: phandle for FSYS sysreg interface, used to control

                 sysreg registers bits for PCIe PHY



required:

  - "#phy-cells"

  - compatible

  - reg

  - samsung,pmu-syscon

  - samsung,fsys-sysreg



additionalProperties: false



examples:

  - |

    pcie_phy: pcie-phy@15680000 {

        compatible = "samsung,exynos5433-pcie-phy";

        reg = <0x15680000 0x1000>;

        samsung,pmu-syscon = <&pmu_system_controller>;

        samsung,fsys-sysreg = <&syscon_fsys>;

        #phy-cells = <0>;

    };

...

drivers/pci/controller/dwc/Kconfig

+8 −2
Original line number Diff line number Diff line
@@ -83,10 +83,15 @@ config PCIE_DW_PLAT_EP 
	  selected.



config PCI_EXYNOS

	bool "Samsung Exynos PCIe controller"

	depends on SOC_EXYNOS5440 || COMPILE_TEST

	tristate "Samsung Exynos PCIe controller"

	depends on ARCH_EXYNOS || COMPILE_TEST

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIE_DW_HOST

	help

	  Enables support for the PCIe controller in the Samsung Exynos SoCs

	  to work in host mode. The PCI controller is based on the DesignWare

	  hardware and therefore the driver re-uses the DesignWare core

	  functions to implement the driver.



config PCI_IMX6

	bool "Freescale i.MX6/7/8 PCIe controller"
@@ -169,6 +174,7 @@ config PCIE_QCOM 
	depends on OF && (ARCH_QCOM || COMPILE_TEST)

	depends on PCI_MSI_IRQ_DOMAIN

	select PCIE_DW_HOST

	select CRC8

	help

	  Say Y here to enable PCIe controller support on Qualcomm SoCs. The

	  PCIe controller uses the DesignWare core plus Qualcomm-specific