Commit ee4871d0 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'remotes/lorenzo/pci/cadence' 

- Make "cdns,max-outbound-regions" optional (Kishon Vijay Abraham I)

- Fix "ti,syscon-pcie-ctrl" DT property to take argument (Kishon Vijay
  Abraham I)

- Add TI J7200 host and endpoint mode DT bindings (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/cadence:
  PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
  dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
  dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  PCI: cadence: Do not error if "cdns,max-outbound-regions" is not found
  dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
parents 00322424 7aa25623

Documentation/devicetree/bindings/pci/cdns-pcie-ep.yaml

+0 −3
Original line number Diff line number Diff line
@@ -20,7 +20,4 @@ properties: 
    maximum: 32

    default: 32



required:

  - cdns,max-outbound-regions



additionalProperties: true

Documentation/devicetree/bindings/pci/ti,j721e-pci-ep.yaml

+15 −8
Original line number Diff line number Diff line
@@ -15,8 +15,14 @@ allOf: 


properties:

  compatible:

    enum:

      - ti,j721e-pcie-ep

    oneOf:

      - description: PCIe EP controller in J7200

        items:

          - const: ti,j7200-pcie-ep

          - const: ti,j721e-pcie-ep

      - description: PCIe EP controller in J721E

        items:

          - const: ti,j721e-pcie-ep



  reg:

    maxItems: 4
@@ -29,9 +35,12 @@ properties: 
      - const: mem



  ti,syscon-pcie-ctrl:

    description: Phandle to the SYSCON entry required for configuring PCIe mode

                 and link speed.

    $ref: /schemas/types.yaml#/definitions/phandle

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_ctrl register offset within SYSCON

    description: Specifier for configuring PCIe mode and link speed.



  power-domains:

    maxItems: 1
@@ -57,7 +66,6 @@ required: 
  - power-domains

  - clocks

  - clock-names

  - cdns,max-outbound-regions

  - dma-coherent

  - max-functions

  - phys
@@ -80,13 +88,12 @@ examples: 
                 <0x00 0x0d000000 0x00 0x00800000>,

                 <0x00 0x10000000 0x00 0x08000000>;

           reg-names = "intd_cfg", "user_cfg", "reg", "mem";

           ti,syscon-pcie-ctrl = <&pcie0_ctrl>;

           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;

           max-link-speed = <3>;

           num-lanes = <2>;

           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

           clocks = <&k3_clks 239 1>;

           clock-names = "fck";

           cdns,max-outbound-regions = <16>;

           max-functions = /bits/ 8 <6>;

           dma-coherent;

           phys = <&serdes0_pcie_link>;

Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml

+20 −7
Original line number Diff line number Diff line
@@ -15,8 +15,14 @@ allOf: 


properties:

  compatible:

    enum:

      - ti,j721e-pcie-host

    oneOf:

      - description: PCIe controller in J7200

        items:

          - const: ti,j7200-pcie-host

          - const: ti,j721e-pcie-host

      - description: PCIe controller in J721E

        items:

          - const: ti,j721e-pcie-host



  reg:

    maxItems: 4
@@ -29,9 +35,12 @@ properties: 
      - const: cfg



  ti,syscon-pcie-ctrl:

    description: Phandle to the SYSCON entry required for configuring PCIe mode

      and link speed.

    $ref: /schemas/types.yaml#/definitions/phandle

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: Phandle to the SYSCON entry

          - description: pcie_ctrl register offset within SYSCON

    description: Specifier for configuring PCIe mode and link speed.



  power-domains:

    maxItems: 1
@@ -48,7 +57,11 @@ properties: 
    const: 0x104c



  device-id:

    const: 0xb00d

    oneOf:

      - items:

          - const: 0xb00d

      - items:

          - const: 0xb00f



  msi-map: true
@@ -90,7 +103,7 @@ examples: 
                  <0x00 0x0d000000 0x00 0x00800000>,

                  <0x00 0x10000000 0x00 0x00001000>;

            reg-names = "intd_cfg", "user_cfg", "reg", "cfg";

            ti,syscon-pcie-ctrl = <&pcie0_ctrl>;

            ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;

            max-link-speed = <3>;

            num-lanes = <2>;

            power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;

drivers/pci/controller/cadence/pci-j721e.c

+19 −9
Original line number Diff line number Diff line
@@ -12,6 +12,7 @@ 
#include <linux/irqchip/chained_irq.h>

#include <linux/irqdomain.h>

#include <linux/mfd/syscon.h>

#include <linux/of.h>

#include <linux/of_device.h>

#include <linux/of_irq.h>

#include <linux/pci.h>
@@ -153,7 +154,8 @@ static const struct cdns_pcie_ops j721e_pcie_ops = { 
	.link_up = j721e_pcie_link_up,

};



static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon)

static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon,

			       unsigned int offset)

{

	struct device *dev = pcie->dev;

	u32 mask = J721E_MODE_RC;
@@ -164,7 +166,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) 
	if (mode == PCI_MODE_RC)

		val = J721E_MODE_RC;



	ret = regmap_update_bits(syscon, 0, mask, val);

	ret = regmap_update_bits(syscon, offset, mask, val);

	if (ret)

		dev_err(dev, "failed to set pcie mode\n");
@@ -172,7 +174,7 @@ static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) 
}



static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie,

				     struct regmap *syscon)

				     struct regmap *syscon, unsigned int offset)

{

	struct device *dev = pcie->dev;

	struct device_node *np = dev->of_node;
@@ -185,7 +187,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 
		link_speed = 2;



	val = link_speed - 1;

	ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val);

	ret = regmap_update_bits(syscon, offset, GENERATION_SEL_MASK, val);

	if (ret)

		dev_err(dev, "failed to set link speed\n");
@@ -193,7 +195,7 @@ static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, 
}



static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie,

				     struct regmap *syscon)

				     struct regmap *syscon, unsigned int offset)

{

	struct device *dev = pcie->dev;

	u32 lanes = pcie->num_lanes;
@@ -201,7 +203,7 @@ static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, 
	int ret;



	val = LANE_COUNT(lanes - 1);

	ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val);

	ret = regmap_update_bits(syscon, offset, LANE_COUNT_MASK, val);

	if (ret)

		dev_err(dev, "failed to set link count\n");
@@ -212,6 +214,8 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 
{

	struct device *dev = pcie->dev;

	struct device_node *node = dev->of_node;

	struct of_phandle_args args;

	unsigned int offset = 0;

	struct regmap *syscon;

	int ret;
@@ -221,19 +225,25 @@ static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) 
		return PTR_ERR(syscon);

	}



	ret = j721e_pcie_set_mode(pcie, syscon);

	/* Do not error out to maintain old DT compatibility */

	ret = of_parse_phandle_with_fixed_args(node, "ti,syscon-pcie-ctrl", 1,

					       0, &args);

	if (!ret)

		offset = args.args[0];



	ret = j721e_pcie_set_mode(pcie, syscon, offset);

	if (ret < 0) {

		dev_err(dev, "Failed to set pci mode\n");

		return ret;

	}



	ret = j721e_pcie_set_link_speed(pcie, syscon);

	ret = j721e_pcie_set_link_speed(pcie, syscon, offset);

	if (ret < 0) {

		dev_err(dev, "Failed to set link speed\n");

		return ret;

	}



	ret = j721e_pcie_set_lane_count(pcie, syscon);

	ret = j721e_pcie_set_lane_count(pcie, syscon, offset);

	if (ret < 0) {

		dev_err(dev, "Failed to set num-lanes\n");

		return ret;

drivers/pci/controller/cadence/pcie-cadence-ep.c

+3 −6
Original line number Diff line number Diff line
@@ -530,12 +530,9 @@ int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) 
	}

	pcie->mem_res = res;



	ret = of_property_read_u32(np, "cdns,max-outbound-regions",

				   &ep->max_regions);

	if (ret < 0) {

		dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");

		return ret;

	}

	ep->max_regions = CDNS_PCIE_MAX_OB;

	of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions);



	ep->ob_addr = devm_kcalloc(dev,

				   ep->max_regions, sizeof(*ep->ob_addr),

				   GFP_KERNEL);