Commit ff8752d7 authored by German Gomez's avatar German Gomez Committed by Arnaldo Carvalho de Melo
Browse files

perf arm-spe: Synthesize SPE instruction events 



Synthesize instruction events for every ARM SPE record.

Arm SPE implements a hardware-based sample period, and perf implements a
software-based one. Add a warning message to inform the user of this.

Signed-off-by: default avatarGerman Gomez <german.gomez@arm.com>
Tested-by: default avatarLeo Yan <leo.yan@linaro.org>
Acked-by: default avatarNamhyung Kim <namhyung@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Link: https://lore.kernel.org/r/20211216152404.52474-1-german.gomez@arm.com


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent a840974e

tools/perf/util/arm-spe.c

+62 −0
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ struct arm_spe { 
	u8				sample_branch;

	u8				sample_remote_access;

	u8				sample_memory;

	u8				sample_instructions;

	u64				instructions_sample_period;



	u64				l1d_miss_id;

	u64				l1d_access_id;
@@ -68,6 +70,7 @@ struct arm_spe { 
	u64				branch_miss_id;

	u64				remote_access_id;

	u64				memory_id;

	u64				instructions_id;



	u64				kernel_start;
@@ -90,6 +93,7 @@ struct arm_spe_queue { 
	u64				time;

	u64				timestamp;

	struct thread			*thread;

	u64				period_instructions;

};



static void arm_spe_dump(struct arm_spe *spe __maybe_unused,
@@ -202,6 +206,7 @@ static struct arm_spe_queue *arm_spe__alloc_queue(struct arm_spe *spe, 
	speq->pid = -1;

	speq->tid = -1;

	speq->cpu = -1;

	speq->period_instructions = 0;



	/* params set */

	params.get_trace = arm_spe_get_trace;
@@ -353,6 +358,35 @@ static int arm_spe__synth_branch_sample(struct arm_spe_queue *speq, 
	return arm_spe_deliver_synth_event(spe, speq, event, &sample);

}



static int arm_spe__synth_instruction_sample(struct arm_spe_queue *speq,

					     u64 spe_events_id, u64 data_src)

{

	struct arm_spe *spe = speq->spe;

	struct arm_spe_record *record = &speq->decoder->record;

	union perf_event *event = speq->event_buf;

	struct perf_sample sample = { .ip = 0, };



	/*

	 * Handles perf instruction sampling period.

	 */

	speq->period_instructions++;

	if (speq->period_instructions < spe->instructions_sample_period)

		return 0;

	speq->period_instructions = 0;



	arm_spe_prep_sample(spe, speq, event, &sample);



	sample.id = spe_events_id;

	sample.stream_id = spe_events_id;

	sample.addr = record->virt_addr;

	sample.phys_addr = record->phys_addr;

	sample.data_src = data_src;

	sample.period = spe->instructions_sample_period;

	sample.weight = record->latency;



	return arm_spe_deliver_synth_event(spe, speq, event, &sample);

}



#define SPE_MEM_TYPE	(ARM_SPE_L1D_ACCESS | ARM_SPE_L1D_MISS | \

			 ARM_SPE_LLC_ACCESS | ARM_SPE_LLC_MISS | \

			 ARM_SPE_REMOTE_ACCESS)
@@ -482,6 +516,12 @@ static int arm_spe_sample(struct arm_spe_queue *speq) 
			return err;

	}



	if (spe->sample_instructions) {

		err = arm_spe__synth_instruction_sample(speq, spe->instructions_id, data_src);

		if (err)

			return err;

	}



	return 0;

}
@@ -1110,7 +1150,29 @@ arm_spe_synth_events(struct arm_spe *spe, struct perf_session *session) 
			return err;

		spe->memory_id = id;

		arm_spe_set_event_name(evlist, id, "memory");

		id += 1;

	}



	if (spe->synth_opts.instructions) {

		if (spe->synth_opts.period_type != PERF_ITRACE_PERIOD_INSTRUCTIONS) {

			pr_warning("Only instruction-based sampling period is currently supported by Arm SPE.\n");

			goto synth_instructions_out;

		}

		if (spe->synth_opts.period > 1)

			pr_warning("Arm SPE has a hardware-based sample period.\n"

				   "Additional instruction events will be discarded by --itrace\n");



		spe->sample_instructions = true;

		attr.config = PERF_COUNT_HW_INSTRUCTIONS;

		attr.sample_period = spe->synth_opts.period;

		spe->instructions_sample_period = attr.sample_period;

		err = arm_spe_synth_event(session, &attr, id);

		if (err)

			return err;

		spe->instructions_id = id;

		arm_spe_set_event_name(evlist, id, "instructions");

	}

synth_instructions_out:



	return 0;

}