Merge tag 'drm-next-20210322' of git://linuxtv.org/pinchartl/media into drm-next (fe8a0578) · Commits · EulixOS / Software / Kernel

Documentation/devicetree/bindings/display/allwinner,sun8i-a83t-dw-hdmi.yaml

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		and CEC.

		These DT bindings follow the Synopsys DWC HDMI TX bindings defined
		in Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
		the following device-specific properties.
		in bridge/synopsys,dw-hdmi.yaml with the following device-specific
		properties.

		maintainers:
		- Chen-Yu Tsai <wens@csie.org>

Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt

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		Synopsys DesignWare HDMI TX Encoder
		===================================

		This document defines device tree properties for the Synopsys DesignWare HDMI
		TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
		specification by itself but is meant to be referenced by platform-specific
		device tree bindings.

		When referenced from platform device tree bindings the properties defined in
		this document are defined as follows. The platform device tree bindings are
		responsible for defining whether each property is required or optional.

		- reg: Memory mapped base address and length of the DWC HDMI TX registers.

		- reg-io-width: Width of the registers specified by the reg property. The
		value is expressed in bytes and must be equal to 1 or 4 if specified. The
		register width defaults to 1 if the property is not present.

		- interrupts: Reference to the DWC HDMI TX interrupt.

		- clocks: References to all the clocks specified in the clock-names property
		as specified in Documentation/devicetree/bindings/clock/clock-bindings.txt.

		- clock-names: The DWC HDMI TX uses the following clocks.

		- "iahb" is the bus clock for either AHB and APB (mandatory).
		- "isfr" is the internal register configuration clock (mandatory).
		- "cec" is the HDMI CEC controller main clock (optional).

		- ports: The connectivity of the DWC HDMI TX with the rest of the system is
		expressed in using ports as specified in the device graph bindings defined
		in Documentation/devicetree/bindings/graph.txt. The numbering of the ports
		is platform-specific.

Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.txt

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		Renesas Gen3 DWC HDMI TX Encoder
		================================

		The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
		with a companion PHY IP.

		These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
		Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
		following device-specific properties.


		Required properties:

		- compatible : Shall contain one or more of
		- "renesas,r8a774a1-hdmi" for R8A774A1 (RZ/G2M) compatible HDMI TX
		- "renesas,r8a774b1-hdmi" for R8A774B1 (RZ/G2N) compatible HDMI TX
		- "renesas,r8a774e1-hdmi" for R8A774E1 (RZ/G2H) compatible HDMI TX
		- "renesas,r8a7795-hdmi" for R8A7795 (R-Car H3) compatible HDMI TX
		- "renesas,r8a7796-hdmi" for R8A7796 (R-Car M3-W) compatible HDMI TX
		- "renesas,r8a77961-hdmi" for R8A77961 (R-Car M3-W+) compatible HDMI TX
		- "renesas,r8a77965-hdmi" for R8A77965 (R-Car M3-N) compatible HDMI TX
		- "renesas,rcar-gen3-hdmi" for the generic R-Car Gen3 and RZ/G2 compatible
		HDMI TX

		When compatible with generic versions, nodes must list the SoC-specific
		version corresponding to the platform first, followed by the
		family-specific version.

		- reg: See dw_hdmi.txt.
		- interrupts: HDMI interrupt number
		- clocks: See dw_hdmi.txt.
		- clock-names: Shall contain "iahb" and "isfr" as defined in dw_hdmi.txt.
		- ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
		corresponding to the video input of the controller and one port numbered 1
		corresponding to its HDMI output, and one port numbered 2 corresponding to
		sound input of the controller. Each port shall have a single endpoint.

		Optional properties:

		- power-domains: Shall reference the power domain that contains the DWC HDMI,
		if any.


		Example:

		hdmi0: hdmi@fead0000 {
		compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
		reg = <0 0xfead0000 0 0x10000>;
		interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
		clock-names = "iahb", "isfr";
		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		dw_hdmi0_in: endpoint {
		remote-endpoint = <&du_out_hdmi0>;
		};
		};
		port@1 {
		reg = <1>;
		rcar_dw_hdmi0_out: endpoint {
		remote-endpoint = <&hdmi0_con>;
		};
		};
		port@2 {
		reg = <2>;
		rcar_dw_hdmi0_sound_in: endpoint {
		remote-endpoint = <&hdmi_sound_out>;
		};
		};
		};
		};

		hdmi0-out {
		compatible = "hdmi-connector";
		label = "HDMI0 OUT";
		type = "a";

		port {
		hdmi0_con: endpoint {
		remote-endpoint = <&rcar_dw_hdmi0_out>;
		};
		};
		};

Documentation/devicetree/bindings/display/bridge/renesas,dw-hdmi.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/bridge/renesas,dw-hdmi.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Renesas R-Car DWC HDMI TX Encoder

		maintainers:
		- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

		description: \|
		The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
		with a companion PHY IP.

		allOf:
		- $ref: synopsys,dw-hdmi.yaml#

		properties:
		compatible:
		items:
		- enum:
		- renesas,r8a774a1-hdmi # for RZ/G2M compatible HDMI TX
		- renesas,r8a774b1-hdmi # for RZ/G2N compatible HDMI TX
		- renesas,r8a774e1-hdmi # for RZ/G2H compatible HDMI TX
		- renesas,r8a7795-hdmi # for R-Car H3 compatible HDMI TX
		- renesas,r8a7796-hdmi # for R-Car M3-W compatible HDMI TX
		- renesas,r8a77961-hdmi # for R-Car M3-W+ compatible HDMI TX
		- renesas,r8a77965-hdmi # for R-Car M3-N compatible HDMI TX
		- const: renesas,rcar-gen3-hdmi

		reg-io-width:
		const: 1

		clocks:
		maxItems: 2

		clock-names:
		maxItems: 2

		ports:
		$ref: /schemas/graph.yaml#/properties/ports

		properties:
		port@0:
		$ref: /schemas/graph.yaml#/properties/port
		description: Parallel RGB input port

		port@1:
		$ref: /schemas/graph.yaml#/properties/port
		description: HDMI output port

		port@2:
		$ref: /schemas/graph.yaml#/properties/port
		description: Sound input port

		required:
		- port@0
		- port@1
		- port@2

		power-domains:
		maxItems: 1

		required:
		- compatible
		- reg
		- clocks
		- clock-names
		- interrupts
		- ports

		unevaluatedProperties: false

		examples:
		- \|
		#include <dt-bindings/clock/r8a7795-cpg-mssr.h>
		#include <dt-bindings/interrupt-controller/irq.h>
		#include <dt-bindings/power/r8a7795-sysc.h>

		hdmi@fead0000 {
		compatible = "renesas,r8a7795-hdmi", "renesas,rcar-gen3-hdmi";
		reg = <0xfead0000 0x10000>;
		interrupts = <0 389 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_CORE R8A7795_CLK_S0D4>, <&cpg CPG_MOD 729>;
		clock-names = "iahb", "isfr";
		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;

		ports {
		#address-cells = <1>;
		#size-cells = <0>;
		port@0 {
		reg = <0>;
		dw_hdmi0_in: endpoint {
		remote-endpoint = <&du_out_hdmi0>;
		};
		};
		port@1 {
		reg = <1>;
		rcar_dw_hdmi0_out: endpoint {
		remote-endpoint = <&hdmi0_con>;
		};
		};
		port@2 {
		reg = <2>;
		rcar_dw_hdmi0_sound_in: endpoint {
		remote-endpoint = <&hdmi_sound_out>;
		};
		};
		};
		};

		hdmi0-out {
		compatible = "hdmi-connector";
		label = "HDMI0 OUT";
		type = "a";

		port {
		hdmi0_con: endpoint {
		remote-endpoint = <&rcar_dw_hdmi0_out>;
		};
		};
		};

		...

Documentation/devicetree/bindings/display/bridge/synopsys,dw-hdmi.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: Common Properties for Synopsys DesignWare HDMI TX Controller

		maintainers:
		- Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

		description: \|
		This document defines device tree properties for the Synopsys DesignWare HDMI
		TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
		binding specification by itself but is meant to be referenced by device tree
		bindings for the platform-specific integrations of the DWC HDMI TX.

		When referenced from platform device tree bindings the properties defined in
		this document are defined as follows. The platform device tree bindings are
		responsible for defining whether each property is required or optional.

		properties:
		reg:
		maxItems: 1

		reg-io-width:
		description:
		Width (in bytes) of the registers specified by the reg property.
		allOf:
		- $ref: /schemas/types.yaml#/definitions/uint32
		- enum: [1, 4]
		default: 1

		clocks:
		minItems: 2
		maxItems: 5
		items:
		- description: The bus clock for either AHB and APB
		- description: The internal register configuration clock
		additionalItems: true

		clock-names:
		minItems: 2
		maxItems: 5
		items:
		- const: iahb
		- const: isfr
		additionalItems: true

		interrupts:
		maxItems: 1

		additionalProperties: true

		...