Commit 2cbcb78c authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge tag 'amd-drm-next-5.13-2021-03-23' of... 

Merge tag 'amd-drm-next-5.13-2021-03-23' of https://gitlab.freedesktop.org/agd5f/linux into drm-next

amd-drm-next-5.13-2021-03-23:

amdgpu:
- Debugfs cleanup
- Various cleanups and spelling fixes
- Flexible array cleanups
- Initial AMD Freesync HDMI
- Display fixes
- 10bpc dithering improvements
- Display ASSR support
- Clean up and unify powerplay and swsmu interfaces
- Vangogh fixes
- Add SMU gfx busy queues for RV/PCO
- PCIE DPM fixes
- S0ix fixes
- GPU metrics data fixes
- DCN secure display support
- Backlight type override
- Add initial support for Aldebaran
- RAS fixes
- Prime fixes for A+A systems
- Reset fixes
- Initial resource cursor support
- Drop legacy IO BAR requirements
- Various power fixes

amdkfd:
- MMU notifier fixes
- APU fixes

radeon:
- Debugfs cleanups
- Flexible array cleanups

UAPI:
- amdgpu: Add a new INFO ioctl interface to query video capabilities
  rather than hardcoding them in userspace.  This allows us to provide
  fine grained asic capabilities (e.g., if a particular part is
  bandwidth limited, we can limit the capabilities).  Proposed userspace:
  https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps
  https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps
- amdkfd: bump the driver version.  There was a problem with reporting
  some RAS features on older versions of the driver. Proposed userspace:
  https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21



Danvet: A bunch of conflicts all over, but it seems to compile ... I
did put the call to dc_allow_idle_optimizations() on a single line
since it looked a bit too jarring to be left alone.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210324040147.1990338-1-alexander.deucher@amd.com
parents 06debd6e 8c44390d

drivers/gpu/drm/amd/amdgpu/Kconfig

+0 −9
Original line number Diff line number Diff line
@@ -34,15 +34,6 @@ config DRM_AMDGPU_USERPTR 
	  This option selects CONFIG_HMM and CONFIG_HMM_MIRROR if it

	  isn't already selected to enabled full userptr support.



config DRM_AMDGPU_GART_DEBUGFS

	bool "Allow GART access through debugfs"

	depends on DRM_AMDGPU

	depends on DEBUG_FS

	default n

	help

	  Selecting this option creates a debugfs file to inspect the mapped

	  pages. Uses more memory for housekeeping, enable only for debugging.



source "drivers/gpu/drm/amd/acp/Kconfig"

source "drivers/gpu/drm/amd/display/Kconfig"

source "drivers/gpu/drm/amd/amdkfd/Kconfig"

drivers/gpu/drm/amd/amdgpu/Makefile

+10 −4
Original line number Diff line number Diff line
@@ -71,7 +71,7 @@ amdgpu-y += \ 
	vi.o mxgpu_vi.o nbio_v6_1.o soc15.o emu_soc.o mxgpu_ai.o nbio_v7_0.o vega10_reg_init.o \

	vega20_reg_init.o nbio_v7_4.o nbio_v2_3.o nv.o navi10_reg_init.o navi14_reg_init.o \

	arct_reg_init.o navi12_reg_init.o mxgpu_nv.o sienna_cichlid_reg_init.o vangogh_reg_init.o \

	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o

	nbio_v7_2.o dimgrey_cavefish_reg_init.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o



# add DF block

amdgpu-y += \
@@ -83,7 +83,8 @@ amdgpu-y += \ 
	gmc_v7_0.o \

	gmc_v8_0.o \

	gfxhub_v1_0.o mmhub_v1_0.o gmc_v9_0.o gfxhub_v1_1.o mmhub_v9_4.o \

	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o

	gfxhub_v2_0.o mmhub_v2_0.o gmc_v10_0.o gfxhub_v2_1.o mmhub_v2_3.o \

	mmhub_v1_7.o



# add UMC block

amdgpu-y += \
@@ -106,7 +107,8 @@ amdgpu-y += \ 
	psp_v3_1.o \

	psp_v10_0.o \

	psp_v11_0.o \

	psp_v12_0.o

	psp_v12_0.o \

	psp_v13_0.o



# add DCE block

amdgpu-y += \
@@ -121,6 +123,7 @@ amdgpu-y += \ 
	gfx_v8_0.o \

	gfx_v9_0.o \

	gfx_v9_4.o \

	gfx_v9_4_2.o \

	gfx_v10_0.o



# add async DMA block
@@ -129,6 +132,7 @@ amdgpu-y += \ 
	sdma_v2_4.o \

	sdma_v3_0.o \

	sdma_v4_0.o \

	sdma_v4_4.o \

	sdma_v5_0.o \

	sdma_v5_2.o
@@ -172,7 +176,8 @@ amdgpu-y += \ 
amdgpu-y += \

	smuio_v9_0.o \

	smuio_v11_0.o \

	smuio_v11_0_6.o

	smuio_v11_0_6.o \

	smuio_v13_0.o



# add amdkfd interfaces

amdgpu-y += amdgpu_amdkfd.o
@@ -187,6 +192,7 @@ amdgpu-y += \ 
	amdgpu_amdkfd_gfx_v8.o \

	amdgpu_amdkfd_gfx_v9.o \

	amdgpu_amdkfd_arcturus.o \

	amdgpu_amdkfd_aldebaran.o \

	amdgpu_amdkfd_gfx_v10.o \

	amdgpu_amdkfd_gfx_v10_3.o

drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.c

0 → 100644
+54 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2020 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include "amdgpu.h"

#include "soc15.h"



#include "soc15_common.h"

#include "aldebaran_ip_offset.h"



int aldebaran_reg_base_init(struct amdgpu_device *adev)

{

	/* HW has more IP blocks,  only initialized the block needed by our driver  */

	uint32_t i;

	for (i = 0 ; i < MAX_INSTANCE ; ++i) {

		adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));

		adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));

		adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));

		adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));

		adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));

		adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));

		adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));

		adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));

		adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));

		adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));

		adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));

		adev->reg_offset[SDMA2_HWIP][i] = (uint32_t *)(&(SDMA2_BASE.instance[i]));

		adev->reg_offset[SDMA3_HWIP][i] = (uint32_t *)(&(SDMA3_BASE.instance[i]));

		adev->reg_offset[SDMA4_HWIP][i] = (uint32_t *)(&(SDMA4_BASE.instance[i]));

		adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));

		adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));

		adev->reg_offset[UMC_HWIP][i] = (uint32_t *)(&(UMC_BASE.instance[i]));

		adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));

	}

	return 0;

}

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+43 −13
Original line number Diff line number Diff line
@@ -124,6 +124,16 @@ struct amdgpu_mgpu_info 
	uint32_t			num_gpu;

	uint32_t			num_dgpu;

	uint32_t			num_apu;



	/* delayed reset_func for XGMI configuration if necessary */

	struct delayed_work		delayed_reset_work;

	bool				pending_reset;

};



struct amdgpu_watchdog_timer

{

	bool timeout_fatal_disable;

	uint32_t period; /* maxCycles = (1 << period), the number of cycles before a timeout */

};



#define AMDGPU_MAX_TIMEOUT_PARAM_LENGTH	256
@@ -177,7 +187,9 @@ extern int amdgpu_compute_multipipe; 
extern int amdgpu_gpu_recovery;

extern int amdgpu_emu_mode;

extern uint amdgpu_smu_memory_pool_size;

extern int amdgpu_smu_pptable_id;

extern uint amdgpu_dc_feature_mask;

extern uint amdgpu_freesync_vid_mode;

extern uint amdgpu_dc_debug_mask;

extern uint amdgpu_dm_abm_level;

extern int amdgpu_backlight;
@@ -185,6 +197,7 @@ extern struct amdgpu_mgpu_info mgpu_info; 
extern int amdgpu_ras_enable;

extern uint amdgpu_ras_mask;

extern int amdgpu_bad_page_threshold;

extern struct amdgpu_watchdog_timer amdgpu_watchdog_timer;

extern int amdgpu_async_gfx_ring;

extern int amdgpu_mcbp;

extern int amdgpu_discovery;
@@ -584,6 +597,19 @@ enum amd_reset_method { 
	AMD_RESET_METHOD_PCI,

};



struct amdgpu_video_codec_info {

	u32 codec_type;

	u32 max_width;

	u32 max_height;

	u32 max_pixels_per_frame;

	u32 max_level;

};



struct amdgpu_video_codecs {

	const u32 codec_count;

	const struct amdgpu_video_codec_info *codec_array;

};



/*

 * ASIC specific functions.

 */
@@ -628,6 +654,9 @@ struct amdgpu_asic_funcs { 
	void (*pre_asic_init)(struct amdgpu_device *adev);

	/* enter/exit umd stable pstate */

	int (*update_umd_stable_pstate)(struct amdgpu_device *adev, bool enter);

	/* query video codecs */

	int (*query_video_codecs)(struct amdgpu_device *adev, bool encode,

				  const struct amdgpu_video_codecs **codecs);

};



/*
@@ -792,12 +821,7 @@ struct amdgpu_device { 
	bool				accel_working;

	struct notifier_block		acpi_nb;

	struct amdgpu_i2c_chan		*i2c_bus[AMDGPU_MAX_I2C_BUS];

	struct amdgpu_debugfs		debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];

	unsigned			debugfs_count;

#if defined(CONFIG_DEBUG_FS)

	struct dentry                   *debugfs_preempt;

	struct dentry			*debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];

#endif

	struct debugfs_blob_wrapper     debugfs_vbios_blob;

	struct amdgpu_atif		*atif;

	struct amdgpu_atcs		atcs;

	struct mutex			srbm_mutex;
@@ -853,8 +877,6 @@ struct amdgpu_device { 
	spinlock_t audio_endpt_idx_lock;

	amdgpu_block_rreg_t		audio_endpt_rreg;

	amdgpu_block_wreg_t		audio_endpt_wreg;

	void __iomem                    *rio_mem;

	resource_size_t			rio_mem_size;

	struct amdgpu_doorbell		doorbell;



	/* clock/pll info */
@@ -897,6 +919,7 @@ struct amdgpu_device { 
	struct amdgpu_irq_src		vupdate_irq;

	struct amdgpu_irq_src		pageflip_irq;

	struct amdgpu_irq_src		hpd_irq;

	struct amdgpu_irq_src		dmub_trace_irq;



	/* rings */

	u64				fence_context;
@@ -1024,6 +1047,7 @@ struct amdgpu_device { 


	int asic_reset_res;

	struct work_struct		xgmi_reset_work;

	struct list_head		reset_list;



	long				gfx_timeout;

	long				sdma_timeout;
@@ -1088,9 +1112,6 @@ void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, 
void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset, uint8_t value);

uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);



u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);

void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);



u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev,

				u32 pcie_index, u32 pcie_data,

				u32 reg_addr);
@@ -1107,6 +1128,15 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, 
bool amdgpu_device_asic_has_dc_support(enum amd_asic_type asic_type);

bool amdgpu_device_has_dc_support(struct amdgpu_device *adev);



int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev,

				  struct amdgpu_job *job,

				  bool *need_full_reset_arg);



int amdgpu_do_asic_reset(struct amdgpu_hive_info *hive,

			  struct list_head *device_list_handle,

			  bool *need_full_reset_arg,

			  bool skip_hw_reset);



int emu_soc_asic_init(struct amdgpu_device *adev);



/*
@@ -1172,8 +1202,6 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
	} while (0)



#define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))

#define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))

#define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))



#define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT

#define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
@@ -1227,6 +1255,7 @@ int emu_soc_asic_init(struct amdgpu_device *adev); 
#define amdgpu_asic_pre_asic_init(adev) (adev)->asic_funcs->pre_asic_init((adev))

#define amdgpu_asic_update_umd_stable_pstate(adev, enter) \

	((adev)->asic_funcs->update_umd_stable_pstate ? (adev)->asic_funcs->update_umd_stable_pstate((adev), (enter)) : 0)

#define amdgpu_asic_query_video_codecs(adev, e, c) (adev)->asic_funcs->query_video_codecs((adev), (e), (c))



#define amdgpu_inc_vram_lost(adev) atomic_inc(&((adev)->vram_lost_counter));
@@ -1247,6 +1276,7 @@ void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, 
					     const u32 array_size);



bool amdgpu_device_supports_atpx(struct drm_device *dev);

int amdgpu_device_mode1_reset(struct amdgpu_device *adev);

bool amdgpu_device_supports_boco(struct drm_device *dev);

bool amdgpu_device_supports_baco(struct drm_device *dev);

bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev,

drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c

+3 −9
Original line number Diff line number Diff line
@@ -44,7 +44,7 @@ int amdgpu_amdkfd_init(void) 
	int ret;



	si_meminfo(&si);

	amdgpu_amdkfd_total_mem_size = si.totalram - si.totalhigh;

	amdgpu_amdkfd_total_mem_size = si.freeram - si.freehigh;

	amdgpu_amdkfd_total_mem_size *= si.mem_unit;



	ret = kgd2kfd_init();
@@ -165,7 +165,8 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *adev) 
					adev->doorbell_index.last_non_cp;

		}



		kgd2kfd_device_init(adev->kfd.dev, adev_to_drm(adev), &gpu_resources);

		adev->kfd.init_complete = kgd2kfd_device_init(adev->kfd.dev,

						adev_to_drm(adev), &gpu_resources);

	}

}
@@ -638,13 +639,6 @@ void amdgpu_amdkfd_set_compute_idle(struct kgd_dev *kgd, bool idle) 
{

	struct amdgpu_device *adev = (struct amdgpu_device *)kgd;



	/* Temp workaround to fix the soft hang observed in certain compute

	 * applications if GFXOFF is enabled.

	 */

	if (adev->asic_type == CHIP_SIENNA_CICHLID) {

		pr_debug("GFXOFF is %s\n", idle ? "enabled" : "disabled");

		amdgpu_gfx_off_ctrl(adev, idle);

	}

	amdgpu_dpm_switch_power_profile(adev,

					PP_SMC_POWER_PROFILE_COMPUTE,

					!idle);