Commit 06debd6e authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2021-03-16' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



Highlights:
- Alderlake S enabling, via topic branch (Aditya, Anusha, Caz, José, Lucas, Matt, Tejas)
- Refactor display code to shrink intel_display.c etc. (Dave)
- Support more gen 9 and Tigerlake PCH combinations (Lyude, Tejas)
- Add eDP MSO support (Jani)

Display:
- Refactor to support multiple PSR instances (Gwan-gyeong)
- Link training debug logging updates (Sean)
- Updates to eDP fixed mode handling (Jani)
- Disable PSR2 on JSL/EHL (Edmund)
- Support DDR5 and LPDDR5 for bandwidth computation (Clint, José)
- Update VBT DP max link rate table (Shawn)
- Disable the QSES check for HDCP2.2 over MST (Juston)
- PSR updates, refactoring, selective fetch (José, Gwan-gyeong)
- Display init sequence refactoring (Lucas)
- Limit LSPCON to gen 9 and 10 platforms (Ankit)
- Fix DDI lane polarity per VBT info (Uma)
- Fix HDMI vswing programming location in mode set (Ville)
- Various display improvements and refactorings and cleanups (Ville)
- Clean up DDI clock routing and readout (Ville)
- Workaround async flip + VT-d corruption on HSW/BDW (Ville)
- SAGV watermark fixes and cleanups (Ville)
- Silence pipe tracepoint WARNs (Ville)

Other:
- Remove require_force_probe protection from RKL, may need to be revisited (Tejas)
- Detect loss of MMIO access (Matt)
- GVT display improvements
- drm/i915: Disable runtime power management during shutdown (Imre)
- Perf/OA updates (Umesh)
- Remove references to struct drm_device.pdev, via topic branch (Thomas)
- Backmerge (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/87v99rnk1g.fsf@intel.com
parents 51c3b916 2b25fb31

arch/x86/kernel/early-quirks.c

+1 −0
Original line number Diff line number Diff line
@@ -551,6 +551,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { 
	INTEL_EHL_IDS(&gen11_early_ops),

	INTEL_TGL_12_IDS(&gen11_early_ops),

	INTEL_RKL_IDS(&gen11_early_ops),

	INTEL_ADLS_IDS(&gen11_early_ops),

};



struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);

drivers/gpu/drm/i915/Makefile

+4 −1
Original line number Diff line number Diff line
@@ -223,7 +223,9 @@ i915-y += \ 
	display/intel_sprite.o \

	display/intel_tc.o \

	display/intel_vga.o \

	display/i9xx_plane.o

	display/i9xx_plane.o \

	display/skl_scaler.o \

	display/skl_universal_plane.o

i915-$(CONFIG_ACPI) += \

	display/intel_acpi.o \

	display/intel_opregion.o
@@ -241,6 +243,7 @@ i915-y += \ 
	display/icl_dsi.o \

	display/intel_crt.o \

	display/intel_ddi.o \

	display/intel_ddi_buf_trans.o \

	display/intel_dp.o \

	display/intel_dp_aux.o \

	display/intel_dp_aux_backlight.o \

drivers/gpu/drm/i915/display/i9xx_plane.c

+119 −4
Original line number Diff line number Diff line
@@ -770,10 +770,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	int num_formats;

	int ret, zpos;



	if (INTEL_GEN(dev_priv) >= 9)

		return skl_universal_plane_create(dev_priv, pipe,

						  PLANE_PRIMARY);



	plane = intel_plane_alloc();

	if (IS_ERR(plane))

		return plane;
@@ -924,3 +920,122 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) 
	return ERR_PTR(ret);

}



static int i9xx_format_to_fourcc(int format)

{

	switch (format) {

	case DISPPLANE_8BPP:

		return DRM_FORMAT_C8;

	case DISPPLANE_BGRA555:

		return DRM_FORMAT_ARGB1555;

	case DISPPLANE_BGRX555:

		return DRM_FORMAT_XRGB1555;

	case DISPPLANE_BGRX565:

		return DRM_FORMAT_RGB565;

	default:

	case DISPPLANE_BGRX888:

		return DRM_FORMAT_XRGB8888;

	case DISPPLANE_RGBX888:

		return DRM_FORMAT_XBGR8888;

	case DISPPLANE_BGRA888:

		return DRM_FORMAT_ARGB8888;

	case DISPPLANE_RGBA888:

		return DRM_FORMAT_ABGR8888;

	case DISPPLANE_BGRX101010:

		return DRM_FORMAT_XRGB2101010;

	case DISPPLANE_RGBX101010:

		return DRM_FORMAT_XBGR2101010;

	case DISPPLANE_BGRA101010:

		return DRM_FORMAT_ARGB2101010;

	case DISPPLANE_RGBA101010:

		return DRM_FORMAT_ABGR2101010;

	case DISPPLANE_RGBX161616:

		return DRM_FORMAT_XBGR16161616F;

	}

}



void

i9xx_get_initial_plane_config(struct intel_crtc *crtc,

			      struct intel_initial_plane_config *plane_config)

{

	struct drm_device *dev = crtc->base.dev;

	struct drm_i915_private *dev_priv = to_i915(dev);

	struct intel_plane *plane = to_intel_plane(crtc->base.primary);

	enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;

	enum pipe pipe;

	u32 val, base, offset;

	int fourcc, pixel_format;

	unsigned int aligned_height;

	struct drm_framebuffer *fb;

	struct intel_framebuffer *intel_fb;



	if (!plane->get_hw_state(plane, &pipe))

		return;



	drm_WARN_ON(dev, pipe != crtc->pipe);



	intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);

	if (!intel_fb) {

		drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");

		return;

	}



	fb = &intel_fb->base;



	fb->dev = dev;



	val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));



	if (INTEL_GEN(dev_priv) >= 4) {

		if (val & DISPPLANE_TILED) {

			plane_config->tiling = I915_TILING_X;

			fb->modifier = I915_FORMAT_MOD_X_TILED;

		}



		if (val & DISPPLANE_ROTATE_180)

			plane_config->rotation = DRM_MODE_ROTATE_180;

	}



	if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B &&

	    val & DISPPLANE_MIRROR)

		plane_config->rotation |= DRM_MODE_REFLECT_X;



	pixel_format = val & DISPPLANE_PIXFORMAT_MASK;

	fourcc = i9xx_format_to_fourcc(pixel_format);

	fb->format = drm_format_info(fourcc);



	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {

		offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane));

		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;

	} else if (INTEL_GEN(dev_priv) >= 4) {

		if (plane_config->tiling)

			offset = intel_de_read(dev_priv,

					       DSPTILEOFF(i9xx_plane));

		else

			offset = intel_de_read(dev_priv,

					       DSPLINOFF(i9xx_plane));

		base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & 0xfffff000;

	} else {

		base = intel_de_read(dev_priv, DSPADDR(i9xx_plane));

	}

	plane_config->base = base;



	val = intel_de_read(dev_priv, PIPESRC(pipe));

	fb->width = ((val >> 16) & 0xfff) + 1;

	fb->height = ((val >> 0) & 0xfff) + 1;



	val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane));

	fb->pitches[0] = val & 0xffffffc0;



	aligned_height = intel_fb_align_height(fb, 0, fb->height);



	plane_config->size = fb->pitches[0] * aligned_height;



	drm_dbg_kms(&dev_priv->drm,

		    "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",

		    crtc->base.name, plane->base.name, fb->width, fb->height,

		    fb->format->cpp[0] * 8, base, fb->pitches[0],

		    plane_config->size);



	plane_config->fb = intel_fb;

}

drivers/gpu/drm/i915/display/i9xx_plane.h

+4 −0
Original line number Diff line number Diff line
@@ -10,6 +10,8 @@ 


enum pipe;

struct drm_i915_private;

struct intel_crtc;

struct intel_initial_plane_config;

struct intel_plane;

struct intel_plane_state;
@@ -21,4 +23,6 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state); 
struct intel_plane *

intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe);



void i9xx_get_initial_plane_config(struct intel_crtc *crtc,

				   struct intel_initial_plane_config *plane_config);

#endif

drivers/gpu/drm/i915/display/icl_dsi.c

+23 −5
Original line number Diff line number Diff line
@@ -35,6 +35,8 @@ 
#include "intel_dsi.h"

#include "intel_panel.h"

#include "intel_vdsc.h"

#include "skl_scaler.h"

#include "skl_universal_plane.h"



static int header_credits_available(struct drm_i915_private *dev_priv,

				    enum transcoder dsi_trans)
@@ -653,6 +655,24 @@ static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder) 
	mutex_unlock(&dev_priv->dpll.lock);

}



static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)

{

	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	bool clock_enabled = false;

	enum phy phy;

	u32 tmp;



	tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);



	for_each_dsi_phy(phy, intel_dsi->phys) {

		if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))

			clock_enabled = true;

	}



	return clock_enabled;

}



static void gen11_dsi_map_pll(struct intel_encoder *encoder,

			      const struct intel_crtc_state *crtc_state)

{
@@ -1488,14 +1508,10 @@ static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi, 
static void gen11_dsi_get_config(struct intel_encoder *encoder,

				 struct intel_crtc_state *pipe_config)

{

	struct drm_i915_private *i915 = to_i915(encoder->base.dev);

	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);



	/* FIXME: adapt icl_ddi_clock_get() for DSI and use that? */

	pipe_config->port_clock = intel_dpll_get_freq(i915,

						      pipe_config->shared_dpll,

						      &pipe_config->dpll_hw_state);

	intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));



	pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;

	if (intel_dsi->dual_link)
@@ -1940,6 +1956,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv) 
	encoder->pipe_mask = ~0;

	encoder->power_domain = POWER_DOMAIN_PORT_DSI;

	encoder->get_power_domains = gen11_dsi_get_power_domains;

	encoder->disable_clock = gen11_dsi_gate_clocks;

	encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;



	/* register DSI connector with DRM subsystem */

	drm_connector_init(dev, connector, &gen11_dsi_connector_funcs,