Commit fcc02c75 authored by Jani Nikula's avatar Jani Nikula
Browse files

drm/i915/irq: add ilk_de_irq_postinstall() 



Add a dedicated de postinstall function.

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/f4a8570881e9be28a2406134b2898b8680f9e765.1691509966.git.jani.nikula@intel.com
parent 1007337f

drivers/gpu/drm/i915/display/intel_display_irq.c

+41 −0
Original line number Diff line number Diff line
@@ -1583,6 +1583,47 @@ void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv) 
		vlv_display_irq_reset(dev_priv);

}



void ilk_de_irq_postinstall(struct drm_i915_private *i915)

{

	struct intel_uncore *uncore = &i915->uncore;

	u32 display_mask, extra_mask;



	if (GRAPHICS_VER(i915) >= 7) {

		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |

				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);

		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |

			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |

			      DE_PLANE_FLIP_DONE_IVB(PLANE_C) |

			      DE_PLANE_FLIP_DONE_IVB(PLANE_B) |

			      DE_PLANE_FLIP_DONE_IVB(PLANE_A) |

			      DE_DP_A_HOTPLUG_IVB);

	} else {

		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |

				DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |

				DE_PIPEA_CRC_DONE | DE_POISON);

		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |

			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |

			      DE_PLANE_FLIP_DONE(PLANE_A) |

			      DE_PLANE_FLIP_DONE(PLANE_B) |

			      DE_DP_A_HOTPLUG);

	}



	if (IS_HASWELL(i915)) {

		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);

		display_mask |= DE_EDP_PSR_INT_HSW;

	}



	if (IS_IRONLAKE_M(i915))

		extra_mask |= DE_PCU_EVENT;



	i915->irq_mask = ~display_mask;



	ibx_irq_postinstall(i915);



	GEN3_IRQ_INIT(uncore, DE, i915->irq_mask,

		      display_mask | extra_mask);

}



void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

drivers/gpu/drm/i915/display/intel_display_irq.h

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ void gen11_display_irq_reset(struct drm_i915_private *i915); 
void ibx_irq_postinstall(struct drm_i915_private *i915);

void vlv_display_irq_postinstall(struct drm_i915_private *i915);

void icp_irq_postinstall(struct drm_i915_private *i915);

void ilk_de_irq_postinstall(struct drm_i915_private *i915);

void gen8_de_irq_postinstall(struct drm_i915_private *i915);

void gen11_de_irq_postinstall(struct drm_i915_private *i915);

void dg1_de_irq_postinstall(struct drm_i915_private *i915);

drivers/gpu/drm/i915/i915_irq.c

+1 −37
Original line number Diff line number Diff line
@@ -772,45 +772,9 @@ static void cherryview_irq_reset(struct drm_i915_private *dev_priv) 


static void ilk_irq_postinstall(struct drm_i915_private *dev_priv)

{

	struct intel_uncore *uncore = &dev_priv->uncore;

	u32 display_mask, extra_mask;



	if (GRAPHICS_VER(dev_priv) >= 7) {

		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |

				DE_PCH_EVENT_IVB | DE_AUX_CHANNEL_A_IVB);

		extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |

			      DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB |

			      DE_PLANE_FLIP_DONE_IVB(PLANE_C) |

			      DE_PLANE_FLIP_DONE_IVB(PLANE_B) |

			      DE_PLANE_FLIP_DONE_IVB(PLANE_A) |

			      DE_DP_A_HOTPLUG_IVB);

	} else {

		display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |

				DE_AUX_CHANNEL_A | DE_PIPEB_CRC_DONE |

				DE_PIPEA_CRC_DONE | DE_POISON);

		extra_mask = (DE_PIPEA_VBLANK | DE_PIPEB_VBLANK |

			      DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN |

			      DE_PLANE_FLIP_DONE(PLANE_A) |

			      DE_PLANE_FLIP_DONE(PLANE_B) |

			      DE_DP_A_HOTPLUG);

	}



	if (IS_HASWELL(dev_priv)) {

		gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);

		display_mask |= DE_EDP_PSR_INT_HSW;

	}



	if (IS_IRONLAKE_M(dev_priv))

		extra_mask |= DE_PCU_EVENT;



	dev_priv->irq_mask = ~display_mask;



	ibx_irq_postinstall(dev_priv);



	gen5_gt_irq_postinstall(to_gt(dev_priv));



	GEN3_IRQ_INIT(uncore, DE, dev_priv->irq_mask,

		      display_mask | extra_mask);

	ilk_de_irq_postinstall(dev_priv);

}



static void valleyview_irq_postinstall(struct drm_i915_private *dev_priv)