Commit fc2e58b8 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "A fairly standard release for SPI with the exception of a change to
  the API for specifying chip selects done in preparation for supporting
  devices with more than one chip select, this required some mechanical
  changes throughout the tree which have been cooking in -next happily
  for a while.

  There's also a new API to allow us to support TPM chips on half duplex
  controllers.

  Summary:

   - Refactoring in preparation for supporting multiple chip selects for
     a single device, needed by some flash devices, which required a
     change in the SPI device API visible throughout the tree

   - Support for hardware assisted interaction with SPI TPMs on half
     duplex controllers, implemented on nVidia Tedra210 QuadSPI

   - Optimisation for large transfers on fsl-cpm devices

   - Cleanups around device property use which fix some sisues with
     fwnode

   - Use of both void remove() and devm_platform_.*ioremap_resource()

   - Support for AMD Pensando Elba, Amlogic A1, Cadence device mode,
     Intel MetorLake-S and StarFive J7110 QuadSPI"

* tag 'spi-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (185 commits)
  spi: bcm63xx: use macro DEFINE_SIMPLE_DEV_PM_OPS
  spi: tegra210-quad: Enable TPM wait polling
  spi: Add TPM HW flow flag
  spi: bcm63xx: remove PM_SLEEP based conditional compilation
  spi: cadence-quadspi: use macro DEFINE_SIMPLE_DEV_PM_OPS
  spi: spi-cadence: Add support for Slave mode
  spi: spi-cadence: Switch to spi_controller structure
  spi: cadence-quadspi: fix suspend-resume implementations
  spi: dw: Add support for AMD Pensando Elba SoC
  spi: dw: Add AMD Pensando Elba SoC SPI Controller
  spi: cadence-quadspi: Disable the SPI before reconfiguring
  spi: cadence-quadspi: Update the read timeout based on the length
  spi: spi-loopback-test: Add module param for iteration length
  spi: add support for Amlogic A1 SPI Flash Controller
  dt-bindings: spi: add Amlogic A1 SPI controller
  spi: fsl-spi: No need to check transfer length versus word size
  spi: fsl-spi: Change mspi_apply_cpu_mode_quirks() to void
  spi: fsl-cpm: Use 16 bit mode for large transfers with even size
  spi: fsl-spi: Re-organise transfer bits_per_word adaptation
  spi: fsl-spi: Fix CPM/QE mode Litte Endian
  ...
parents 1c15ca4e cc5f6fa4

Documentation/devicetree/bindings/spi/amlogic,a1-spifc.yaml

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+41 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/spi/amlogic,a1-spifc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Amlogic A1 SPI Flash Controller



maintainers:

  - Martin Kurbanov <mmkurbanov@sberdevices.ru>



allOf:

  - $ref: spi-controller.yaml#



properties:

  compatible:

    enum:

      - amlogic,a1-spifc



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



required:

  - compatible

  - reg

  - clocks



unevaluatedProperties: false



examples:

  - |

    spi@fd000400 {

        compatible = "amlogic,a1-spifc";

        reg = <0xfd000400 0x290>;

        clocks = <&clkc_clkid_spifc>;

        #address-cells = <1>;

        #size-cells = <0>;

    };

Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml

+33 −4
Original line number Diff line number Diff line
@@ -19,6 +19,33 @@ allOf: 
    then:

      required:

        - power-domains

  - if:

      properties:

        compatible:

          contains:

            const: starfive,jh7110-qspi

    then:

      properties:

        resets:

          minItems: 2

          maxItems: 3



        reset-names:

          minItems: 2

          maxItems: 3

          items:

            enum: [ qspi, qspi-ocp, rstc_ref ]



    else:

      properties:

        resets:

          maxItems: 2



        reset-names:

          minItems: 1

          maxItems: 2

          items:

            enum: [ qspi, qspi-ocp ]



properties:

  compatible:
@@ -30,6 +57,7 @@ properties: 
              - intel,lgm-qspi

              - xlnx,versal-ospi-1.0

              - intel,socfpga-qspi

              - starfive,jh7110-qspi

          - const: cdns,qspi-nor

      - const: cdns,qspi-nor
@@ -79,13 +107,14 @@ properties: 
    maxItems: 1



  resets:

    maxItems: 2

    minItems: 2

    maxItems: 3



  reset-names:

    minItems: 1

    maxItems: 2

    minItems: 2

    maxItems: 3

    items:

      enum: [ qspi, qspi-ocp ]

      enum: [ qspi, qspi-ocp, rstc_ref ]



required:

  - compatible

Documentation/devicetree/bindings/spi/renesas,sh-msiof.yaml

+19 −4
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@@ -149,23 +149,38 @@ required: 
  - compatible

  - reg

  - interrupts

  - clocks

  - power-domains

  - '#address-cells'

  - '#size-cells'



if:

  not:

    properties:

      compatible:

        contains:

          const: renesas,sh-mobile-msiof

then:

  required:

    - resets



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/r8a7791-clock.h>

    #include <dt-bindings/interrupt-controller/irq.h>

    #include <dt-bindings/clock/r8a7791-cpg-mssr.h>

    #include <dt-bindings/interrupt-controller/arm-gic.h>

    #include <dt-bindings/power/r8a7791-sysc.h>



    msiof0: spi@e6e20000 {

        compatible = "renesas,msiof-r8a7791", "renesas,rcar-gen2-msiof";

        reg = <0xe6e20000 0x0064>;

        interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;

        interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;

        clocks = <&cpg CPG_MOD 000>;

        dmas = <&dmac0 0x51>, <&dmac0 0x52>;

        dma-names = "tx", "rx";

        power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;

        resets = <&cpg 0>;

        #address-cells = <1>;

        #size-cells = <0>;

    };

Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml

+19 −0
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@@ -37,6 +37,17 @@ allOf: 
    else:

      required:

        - interrupts

  - if:

      properties:

        compatible:

          contains:

            const: amd,pensando-elba-spi

    then:

      required:

        - amd,pensando-elba-syscon

    else:

      properties:

        amd,pensando-elba-syscon: false



properties:

  compatible:
@@ -63,6 +74,8 @@ properties: 
        const: intel,keembay-ssi

      - description: Intel Thunder Bay SPI Controller

        const: intel,thunderbay-ssi

      - description: AMD Pensando Elba SoC SPI Controller

        const: amd,pensando-elba-spi

      - description: Baikal-T1 SPI Controller

        const: baikal,bt1-ssi

      - description: Baikal-T1 System Boot SPI Controller
@@ -136,6 +149,12 @@ properties: 
      of the designware controller, and the upper limit is also subject to

      controller configuration.



  amd,pensando-elba-syscon:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    description:

      Block address to control SPI chip-selects. The Elba SoC system controller

      provides an interface to override the native DWC SSI CS control.



patternProperties:

  "^.*@[0-9a-f]+$":

    type: object

Documentation/spi/spi-summary.rst

+10 −13
Original line number Diff line number Diff line
@@ -178,10 +178,10 @@ shows up in sysfs in several locations:: 


   /sys/bus/spi/drivers/D ... driver for one or more spi*.* devices



   /sys/class/spi_master/spiB ... symlink (or actual device node) to

	a logical node which could hold class related state for the SPI

	master controller managing bus "B".  All spiB.* devices share one

	physical SPI bus segment, with SCLK, MOSI, and MISO.

   /sys/class/spi_master/spiB ... symlink to a logical node which could hold

	class related state for the SPI master controller managing bus "B".

	All spiB.* devices share one physical SPI bus segment, with SCLK,

	MOSI, and MISO.



   /sys/devices/.../CTLR/slave ... virtual file for (un)registering the

	slave device for an SPI slave controller.
@@ -191,16 +191,13 @@ shows up in sysfs in several locations:: 
	Reading from this file shows the name of the slave device ("(null)"

	if not registered).



   /sys/class/spi_slave/spiB ... symlink (or actual device node) to

	a logical node which could hold class related state for the SPI

	slave controller on bus "B".  When registered, a single spiB.*

	device is present here, possible sharing the physical SPI bus

	segment with other SPI slave devices.

   /sys/class/spi_slave/spiB ... symlink to a logical node which could hold

	class related state for the SPI slave controller on bus "B".  When

	registered, a single spiB.* device is present here, possible sharing

	the physical SPI bus segment with other SPI slave devices.



Note that the actual location of the controller's class state depends

on whether you enabled CONFIG_SYSFS_DEPRECATED or not.  At this time,

the only class-specific state is the bus number ("B" in "spiB"), so

those /sys/class entries are only useful to quickly identify busses.

At this time, the only class-specific state is the bus number ("B" in "spiB"),

so those /sys/class entries are only useful to quickly identify busses.





How does board-specific init code declare SPI devices?