Commit 1c15ca4e authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound 

Pull sound updates from Takashi Iwai:
 "At this time, it's an interesting mixture of changes for both old and
  new stuff. Majority of changes are about ASoC (lots of systematic
  changes for converting remove callbacks to void, and cleanups), while
  we got the fixes and the enhancements of very old PCI cards, too.

  Here are some highlights:

  ALSA/ASoC Core:
   - Continued effort of more ASoC core cleanups
   - Minor improvements for XRUN handling in indirect PCM helpers
   - Code refactoring of PCM core code

  ASoC:
   - Continued feature and simplification work on SOF, including
     addition of a no-DSP mode for bringup, HDA MLink and extensions to
     the IPC4 protocol
   - Hibernation support for CS35L45
   - More DT binding conversions
   - Support for Cirrus Logic CS35L56, Freescale QMC, Maxim MAX98363,
     nVidia systems with MAX9809x and RT5631, Realtek RT712, Renesas
     R-Car Gen4, Rockchip RK3588 and TI TAS5733

  ALSA:
   - Lots of works for legacy emu10k1 and ymfpci PCI drivers
   - PCM kselftest fixes and enhancements"

* tag 'sound-6.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (586 commits)
  ALSA: emu10k1: use high-level I/O in set_filterQ()
  ALSA: emu10k1: use high-level I/O functions also during init
  ALSA: emu10k1: fix error handling in snd_audigy_i2c_volume_put()
  ALSA: emu10k1: don't stop DSP in _snd_emu10k1_{,audigy_}init_efx()
  ALSA: emu10k1: fix SNDRV_EMU10K1_IOCTL_SINGLE_STEP
  ALSA: emu10k1: skip Sound Blaster-specific hacks for E-MU cards
  ALSA: emu10k1: fixup DSP defines
  ALSA: emu10k1: pull in some register definitions from kX-project
  ALSA: emu10k1: remove some bogus defines
  ALSA: emu10k1: eliminate some unused defines
  ALSA: emu10k1: fix lineup of EMU_HANA_* defines
  ALSA: emu10k1: comment updates
  ALSA: emu10k1: fix snd_emu1010_fpga_read() input masking for rev2 cards
  ALSA: emu10k1: remove unused emu->pcm_playback_efx_substream field
  ALSA: emu10k1: remove unused `resume` parameter from snd_emu10k1_init()
  ALSA: emu10k1: minor optimizations
  ALSA: emu10k1: remove remaining cruft from snd_emu10k1_emu1010_init()
  ALSA: emu10k1: remove apparently pointless EMU_HANA_OPTION_CARDS reads
  ALSA: emu10k1: remove apparently pointless FPGA reads
  ALSA: emu10k1: stop doing weird things with HCFG in snd_emu10k1_emu1010_init()
  ...
parents 34b62f18 baa6584a

Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PowerQUICC CPM QUICC Multichannel Controller (QMC)



maintainers:

  - Herve Codina <herve.codina@bootlin.com>



description:

  The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one

  serial controller using the same TDM physical interface routed from TSA.



properties:

  compatible:

    items:

      - enum:

          - fsl,mpc885-scc-qmc

          - fsl,mpc866-scc-qmc

      - const: fsl,cpm1-scc-qmc



  reg:

    items:

      - description: SCC (Serial communication controller) register base

      - description: SCC parameter ram base

      - description: Dual port ram base



  reg-names:

    items:

      - const: scc_regs

      - const: scc_pram

      - const: dpram



  interrupts:

    maxItems: 1

    description: SCC interrupt line in the CPM interrupt controller



  fsl,tsa-serial:

    $ref: /schemas/types.yaml#/definitions/phandle-array

    items:

      - items:

          - description: phandle to TSA node

          - enum: [1, 2, 3]

            description: |

              TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these

              values)

               - 1: SCC2

               - 2: SCC3

               - 3: SCC4

    description:

      Should be a phandle/number pair. The phandle to TSA node and the TSA

      serial interface to use.



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  '^channel@([0-9]|[1-5][0-9]|6[0-3])$':

    description:

      A channel managed by this controller

    type: object



    properties:

      reg:

        minimum: 0

        maximum: 63

        description:

          The channel number



      fsl,operational-mode:

        $ref: /schemas/types.yaml#/definitions/string

        enum: [transparent, hdlc]

        default: transparent

        description: |

          The channel operational mode

            - hdlc: The channel handles HDLC frames

            - transparent: The channel handles raw data without any processing



      fsl,reverse-data:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          The bit order as seen on the channels is reversed,

          transmitting/receiving the MSB of each octet first.

          This flag is used only in 'transparent' mode.



      fsl,tx-ts-mask:

        $ref: /schemas/types.yaml#/definitions/uint64

        description:

          Channel assigned Tx time-slots within the Tx time-slots routed by the

          TSA to this cell.



      fsl,rx-ts-mask:

        $ref: /schemas/types.yaml#/definitions/uint64

        description:

          Channel assigned Rx time-slots within the Rx time-slots routed by the

          TSA to this cell.



    required:

      - reg

      - fsl,tx-ts-mask

      - fsl,rx-ts-mask



required:

  - compatible

  - reg

  - reg-names

  - interrupts

  - fsl,tsa-serial

  - '#address-cells'

  - '#size-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/soc/cpm1-fsl,tsa.h>



    qmc@a60 {

        compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";

        reg = <0xa60 0x20>,

              <0x3f00 0xc0>,

              <0x2000 0x1000>;

        reg-names = "scc_regs", "scc_pram", "dpram";

        interrupts = <27>;

        interrupt-parent = <&CPM_PIC>;



        #address-cells = <1>;

        #size-cells = <0>;



        fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;



        channel@16 {

            /* Ch16 : First 4 even TS from all routed from TSA */

            reg = <16>;

            fsl,mode = "transparent";

            fsl,reverse-data;

            fsl,tx-ts-mask = <0x00000000 0x000000aa>;

            fsl,rx-ts-mask = <0x00000000 0x000000aa>;

        };



        channel@17 {

            /* Ch17 : First 4 odd TS from all routed from TSA */

            reg = <17>;

            fsl,mode = "transparent";

            fsl,reverse-data;

            fsl,tx-ts-mask = <0x00000000 0x00000055>;

            fsl,rx-ts-mask = <0x00000000 0x00000055>;

        };



        channel@19 {

            /* Ch19 : 8 TS (TS 8..15) from all routed from TSA */

            reg = <19>;

            fsl,mode = "hdlc";

            fsl,tx-ts-mask = <0x00000000 0x0000ff00>;

            fsl,rx-ts-mask = <0x00000000 0x0000ff00>;

        };

    };

Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: PowerQUICC CPM Time-slot assigner (TSA) controller



maintainers:

  - Herve Codina <herve.codina@bootlin.com>



description:

  The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.

  Its purpose is to route some TDM time-slots to other internal serial

  controllers.



properties:

  compatible:

    items:

      - enum:

          - fsl,mpc885-tsa

          - fsl,mpc866-tsa

      - const: fsl,cpm1-tsa



  reg:

    items:

      - description: SI (Serial Interface) register base

      - description: SI RAM base



  reg-names:

    items:

      - const: si_regs

      - const: si_ram



  '#address-cells':

    const: 1



  '#size-cells':

    const: 0



patternProperties:

  '^tdm@[0-1]$':

    description:

      The TDM managed by this controller

    type: object



    additionalProperties: false



    properties:

      reg:

        minimum: 0

        maximum: 1

        description:

          The TDM number for this TDM, 0 for TDMa and 1 for TDMb



      fsl,common-rxtx-pins:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          The hardware can use four dedicated pins for Tx clock, Tx sync, Rx

          clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.

          Without the 'fsl,common-rxtx-pins' property, the four pins are used.

          With the 'fsl,common-rxtx-pins' property, two pins are used.



      clocks:

        minItems: 2

        items:

          - description: External clock connected to L1RSYNC pin

          - description: External clock connected to L1RCLK pin

          - description: External clock connected to L1TSYNC pin

          - description: External clock connected to L1TCLK pin



      clock-names:

        minItems: 2

        items:

          - const: l1rsync

          - const: l1rclk

          - const: l1tsync

          - const: l1tclk



      fsl,rx-frame-sync-delay-bits:

        enum: [0, 1, 2, 3]

        default: 0

        description: |

          Receive frame sync delay in number of bits.

          Indicates the delay between the Rx sync and the first bit of the Rx

          frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.



      fsl,tx-frame-sync-delay-bits:

        enum: [0, 1, 2, 3]

        default: 0

        description: |

          Transmit frame sync delay in number of bits.

          Indicates the delay between the Tx sync and the first bit of the Tx

          frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.



      fsl,clock-falling-edge:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Data is sent on falling edge of the clock (and received on the rising

          edge). If 'clock-falling-edge' is not present, data is sent on the

          rising edge (and received on the falling edge).



      fsl,fsync-rising-edge:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          Frame sync pulses are sampled with the rising edge of the channel

          clock. If 'fsync-rising-edge' is not present, pulses are sampled with

          the falling edge.



      fsl,double-speed-clock:

        $ref: /schemas/types.yaml#/definitions/flag

        description:

          The channel clock is twice the data rate.



    patternProperties:

      '^fsl,[rt]x-ts-routes$':

        $ref: /schemas/types.yaml#/definitions/uint32-matrix

        description: |

          A list of tuple that indicates the Tx or Rx time-slots routes.

        items:

          items:

            - description:

                The number of time-slots

              minimum: 1

              maximum: 64

            - description: |

                The source (Tx) or destination (Rx) serial interface

                (dt-bindings/soc/cpm1-fsl,tsa.h defines these values)

                 - 0: No destination

                 - 1: SCC2

                 - 2: SCC3

                 - 3: SCC4

                 - 4: SMC1

                 - 5: SMC2

              enum: [0, 1, 2, 3, 4, 5]

        minItems: 1

        maxItems: 64



    allOf:

      # If fsl,common-rxtx-pins is present, only 2 clocks are needed.

      # Else, the 4 clocks must be present.

      - if:

          required:

            - fsl,common-rxtx-pins

        then:

          properties:

            clocks:

              maxItems: 2

            clock-names:

              maxItems: 2

        else:

          properties:

            clocks:

              minItems: 4

            clock-names:

              minItems: 4



    required:

      - reg

      - clocks

      - clock-names



required:

  - compatible

  - reg

  - reg-names

  - '#address-cells'

  - '#size-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/soc/cpm1-fsl,tsa.h>



    tsa@ae0 {

        compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";

        reg = <0xae0 0x10>,

              <0xc00 0x200>;

        reg-names = "si_regs", "si_ram";



        #address-cells = <1>;

        #size-cells = <0>;



        tdm@0 {

            /* TDMa */

            reg = <0>;



            clocks = <&clk_l1rsynca>, <&clk_l1rclka>;

            clock-names = "l1rsync", "l1rclk";



            fsl,common-rxtx-pins;

            fsl,fsync-rising-edge;



            fsl,tx-ts-routes = <2 0>,             /* TS 0..1 */

                           <24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */

                           <1 0>,                 /* TS 26 */

                           <5 FSL_CPM_TSA_SCC3>;  /* TS 27..31 */



            fsl,rx-ts-routes = <2 0>,             /* TS 0..1 */

                           <24 FSL_CPM_TSA_SCC4>, /* 2..25 */

                           <1 0>,                 /* TS 26 */

                           <5 FSL_CPM_TSA_SCC3>;  /* TS 27..31 */

        };

    };

Documentation/devicetree/bindings/sound/adi,adau1372.yaml

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@@ -32,7 +32,7 @@ properties: 
    maxItems: 1



  clock-names:

    const: "mclk"

    const: mclk



  powerdown-gpios:

    description: GPIO used for hardware power-down.

Documentation/devicetree/bindings/sound/adi,adau17x1.txt

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Analog Devices ADAU1361/ADAU1461/ADAU1761/ADAU1961/ADAU1381/ADAU1781



Required properties:



 - compatible:		Should contain one of the following:

			"adi,adau1361"

			"adi,adau1461"

			"adi,adau1761"

			"adi,adau1961"

			"adi,adau1381"

			"adi,adau1781"



 - reg:			The i2c address. Value depends on the state of ADDR0

			and ADDR1, as wired in hardware.



Optional properties:

 - clock-names:		If provided must be "mclk".

 - clocks:		phandle + clock-specifiers for the clock that provides

			the audio master clock for the device.



Examples:

#include <dt-bindings/sound/adau17x1.h>



	i2c_bus {

		adau1361@38 {

			compatible = "adi,adau1761";

			reg = <0x38>;



			clock-names = "mclk";

			clocks = <&audio_clock>;

		};

	};

Documentation/devicetree/bindings/sound/adi,adau17x1.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/sound/adi,adau17x1.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Analog Devices ADAU1361/ADAU1461/ADAU1761/ADAU1961/ADAU1381/ADAU1781 Codec



maintainers:

  - Lars-Peter Clausen <lars@metafoo.de>



properties:

  compatible:

    enum:

      - adi,adau1361

      - adi,adau1381

      - adi,adau1461

      - adi,adau1761

      - adi,adau1781

      - adi,adau1961



  reg:

    maxItems: 1

    description:

      The i2c address. Value depends on the state of ADDR0 and ADDR1,

      as wired in hardware.



  clock-names:

    const: mclk



  clocks:

    items:

      - description: provides the audio master clock for the device.



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    i2c {

      #address-cells = <1>;

      #size-cells = <0>;

      audio-codec@38 {

        compatible = "adi,adau1761";

        reg = <0x38>;

        clock-names = "mclk";

        clocks = <&audio_clock>;

      };

    };