Merge tag 'asoc-v6.4' of... (baa6584a) · Commits · EulixOS / Software / Kernel

.mailmap

+9 −1

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		@@ -136,6 +136,9 @@ Erik Kaneda <erik.kaneda@intel.com> <erik.schmauss@intel.com>
		Eugen Hristev <eugen.hristev@collabora.com> <eugen.hristev@microchip.com>
		Evgeniy Polyakov <johnpol@2ka.mipt.ru>
		Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> <ezequiel@collabora.com>
		Faith Ekstrand <faith.ekstrand@collabora.com> <jason@jlekstrand.net>
		Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@intel.com>
		Faith Ekstrand <faith.ekstrand@collabora.com> <jason.ekstrand@collabora.com>
		Felipe W Damasio <felipewd@terra.com.br>
		Felix Kuhling <fxkuehl@gmx.de>
		Felix Moeller <felix@derklecks.de>
		@@ -306,6 +309,8 @@ Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
		Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>
		Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
		Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
		Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@mellanox.com>
		Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@nvidia.com>
		Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
		Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
		Mayuresh Janorkar <mayur@ti.com>
		@@ -411,7 +416,10 @@ Shuah Khan <shuah@kernel.org> <shuah.kh@samsung.com>
		Simon Arlott <simon@octiron.net> <simon@fire.lp0.eu>
		Simon Kelley <simon@thekelleys.org.uk>
		Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
		Stephen Hemminger <shemminger@osdl.org>
		Stephen Hemminger <stephen@networkplumber.org> <shemminger@linux-foundation.org>
		Stephen Hemminger <stephen@networkplumber.org> <shemminger@osdl.org>
		Stephen Hemminger <stephen@networkplumber.org> <sthemmin@microsoft.com>
		Stephen Hemminger <stephen@networkplumber.org> <sthemmin@vyatta.com>
		Steve Wise <larrystevenwise@gmail.com> <swise@chelsio.com>
		Steve Wise <larrystevenwise@gmail.com> <swise@opengridcomputing.com>
		Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>

Documentation/ABI/stable/sysfs-block

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		@@ -705,6 +705,15 @@ Description:
		zoned will report "none".


		What: /sys/block/<disk>/hidden
		Date: March 2023
		Contact: linux-block@vger.kernel.org
		Description:
		[RO] the block device is hidden. it doesn’t produce events, and
		can’t be opened from userspace or using blkdev_get*.
		Used for the underlying components of multipath devices.


		What: /sys/block/<disk>/stat
		Date: February 2008
		Contact: Jerome Marchand <jmarchan@redhat.com>

Documentation/bpf/bpf_devel_QA.rst

+5 −9

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		@@ -7,8 +7,8 @@ workflows related to reporting bugs, submitting patches, and queueing
		patches for stable kernels.

		For general information about submitting patches, please refer to
		`Documentation/process/`_. This document only describes additional specifics
		related to BPF.
		Documentation/process/submitting-patches.rst. This document only describes
		additional specifics related to BPF.

		.. contents::
		:local:
		@@ -461,15 +461,15 @@ needed::

		$ sudo make run_tests

		See the kernels selftest `Documentation/dev-tools/kselftest.rst`_
		document for further documentation.
		See :doc:`kernel selftest documentation </dev-tools/kselftest>`
		for details.

		To maximize the number of tests passing, the .config of the kernel
		under test should match the config file fragment in
		tools/testing/selftests/bpf as closely as possible.

		Finally to ensure support for latest BPF Type Format features -
		discussed in `Documentation/bpf/btf.rst`_ - pahole version 1.16
		discussed in Documentation/bpf/btf.rst - pahole version 1.16
		is required for kernels built with CONFIG_DEBUG_INFO_BTF=y.
		pahole is delivered in the dwarves package or can be built
		from source at
		@@ -684,12 +684,8 @@ when:


		.. Links
		.. _Documentation/process/: https://www.kernel.org/doc/html/latest/process/
		.. _netdev-FAQ: Documentation/process/maintainer-netdev.rst
		.. _selftests:
		https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/tools/testing/selftests/bpf/
		.. _Documentation/dev-tools/kselftest.rst:
		https://www.kernel.org/doc/html/latest/dev-tools/kselftest.html
		.. _Documentation/bpf/btf.rst: btf.rst

		Happy BPF hacking!

Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: PowerQUICC CPM QUICC Multichannel Controller (QMC)

		maintainers:
		- Herve Codina <herve.codina@bootlin.com>

		description:
		The QMC (QUICC Multichannel Controller) emulates up to 64 channels within one
		serial controller using the same TDM physical interface routed from TSA.

		properties:
		compatible:
		items:
		- enum:
		- fsl,mpc885-scc-qmc
		- fsl,mpc866-scc-qmc
		- const: fsl,cpm1-scc-qmc

		reg:
		items:
		- description: SCC (Serial communication controller) register base
		- description: SCC parameter ram base
		- description: Dual port ram base

		reg-names:
		items:
		- const: scc_regs
		- const: scc_pram
		- const: dpram

		interrupts:
		maxItems: 1
		description: SCC interrupt line in the CPM interrupt controller

		fsl,tsa-serial:
		$ref: /schemas/types.yaml#/definitions/phandle-array
		items:
		- items:
		- description: phandle to TSA node
		- enum: [1, 2, 3]
		description: \|
		TSA serial interface (dt-bindings/soc/cpm1-fsl,tsa.h defines these
		values)
		- 1: SCC2
		- 2: SCC3
		- 3: SCC4
		description:
		Should be a phandle/number pair. The phandle to TSA node and the TSA
		serial interface to use.

		'#address-cells':
		const: 1

		'#size-cells':
		const: 0

		patternProperties:
		'^channel@([0-9]\|[1-5][0-9]\|6[0-3])$':
		description:
		A channel managed by this controller
		type: object

		properties:
		reg:
		minimum: 0
		maximum: 63
		description:
		The channel number

		fsl,operational-mode:
		$ref: /schemas/types.yaml#/definitions/string
		enum: [transparent, hdlc]
		default: transparent
		description: \|
		The channel operational mode
		- hdlc: The channel handles HDLC frames
		- transparent: The channel handles raw data without any processing

		fsl,reverse-data:
		$ref: /schemas/types.yaml#/definitions/flag
		description:
		The bit order as seen on the channels is reversed,
		transmitting/receiving the MSB of each octet first.
		This flag is used only in 'transparent' mode.

		fsl,tx-ts-mask:
		$ref: /schemas/types.yaml#/definitions/uint64
		description:
		Channel assigned Tx time-slots within the Tx time-slots routed by the
		TSA to this cell.

		fsl,rx-ts-mask:
		$ref: /schemas/types.yaml#/definitions/uint64
		description:
		Channel assigned Rx time-slots within the Rx time-slots routed by the
		TSA to this cell.

		required:
		- reg
		- fsl,tx-ts-mask
		- fsl,rx-ts-mask

		required:
		- compatible
		- reg
		- reg-names
		- interrupts
		- fsl,tsa-serial
		- '#address-cells'
		- '#size-cells'

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/soc/cpm1-fsl,tsa.h>

		qmc@a60 {
		compatible = "fsl,mpc885-scc-qmc", "fsl,cpm1-scc-qmc";
		reg = <0xa60 0x20>,
		<0x3f00 0xc0>,
		<0x2000 0x1000>;
		reg-names = "scc_regs", "scc_pram", "dpram";
		interrupts = <27>;
		interrupt-parent = <&CPM_PIC>;

		#address-cells = <1>;
		#size-cells = <0>;

		fsl,tsa-serial = <&tsa FSL_CPM_TSA_SCC4>;

		channel@16 {
		/* Ch16 : First 4 even TS from all routed from TSA */
		reg = <16>;
		fsl,mode = "transparent";
		fsl,reverse-data;
		fsl,tx-ts-mask = <0x00000000 0x000000aa>;
		fsl,rx-ts-mask = <0x00000000 0x000000aa>;
		};

		channel@17 {
		/* Ch17 : First 4 odd TS from all routed from TSA */
		reg = <17>;
		fsl,mode = "transparent";
		fsl,reverse-data;
		fsl,tx-ts-mask = <0x00000000 0x00000055>;
		fsl,rx-ts-mask = <0x00000000 0x00000055>;
		};

		channel@19 {
		/* Ch19 : 8 TS (TS 8..15) from all routed from TSA */
		reg = <19>;
		fsl,mode = "hdlc";
		fsl,tx-ts-mask = <0x00000000 0x0000ff00>;
		fsl,rx-ts-mask = <0x00000000 0x0000ff00>;
		};
		};

Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml

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		# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
		%YAML 1.2
		---
		$id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml#
		$schema: http://devicetree.org/meta-schemas/core.yaml#

		title: PowerQUICC CPM Time-slot assigner (TSA) controller

		maintainers:
		- Herve Codina <herve.codina@bootlin.com>

		description:
		The TSA is the time-slot assigner that can be found on some PowerQUICC SoC.
		Its purpose is to route some TDM time-slots to other internal serial
		controllers.

		properties:
		compatible:
		items:
		- enum:
		- fsl,mpc885-tsa
		- fsl,mpc866-tsa
		- const: fsl,cpm1-tsa

		reg:
		items:
		- description: SI (Serial Interface) register base
		- description: SI RAM base

		reg-names:
		items:
		- const: si_regs
		- const: si_ram

		'#address-cells':
		const: 1

		'#size-cells':
		const: 0

		patternProperties:
		'^tdm@[0-1]$':
		description:
		The TDM managed by this controller
		type: object

		additionalProperties: false

		properties:
		reg:
		minimum: 0
		maximum: 1
		description:
		The TDM number for this TDM, 0 for TDMa and 1 for TDMb

		fsl,common-rxtx-pins:
		$ref: /schemas/types.yaml#/definitions/flag
		description:
		The hardware can use four dedicated pins for Tx clock, Tx sync, Rx
		clock and Rx sync or use only two pins, Tx/Rx clock and Tx/Rx sync.
		Without the 'fsl,common-rxtx-pins' property, the four pins are used.
		With the 'fsl,common-rxtx-pins' property, two pins are used.

		clocks:
		minItems: 2
		items:
		- description: External clock connected to L1RSYNC pin
		- description: External clock connected to L1RCLK pin
		- description: External clock connected to L1TSYNC pin
		- description: External clock connected to L1TCLK pin

		clock-names:
		minItems: 2
		items:
		- const: l1rsync
		- const: l1rclk
		- const: l1tsync
		- const: l1tclk

		fsl,rx-frame-sync-delay-bits:
		enum: [0, 1, 2, 3]
		default: 0
		description: \|
		Receive frame sync delay in number of bits.
		Indicates the delay between the Rx sync and the first bit of the Rx
		frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.

		fsl,tx-frame-sync-delay-bits:
		enum: [0, 1, 2, 3]
		default: 0
		description: \|
		Transmit frame sync delay in number of bits.
		Indicates the delay between the Tx sync and the first bit of the Tx
		frame. 0 for no bit delay. 1, 2 or 3 for 1, 2 or 3 bits delay.

		fsl,clock-falling-edge:
		$ref: /schemas/types.yaml#/definitions/flag
		description:
		Data is sent on falling edge of the clock (and received on the rising
		edge). If 'clock-falling-edge' is not present, data is sent on the
		rising edge (and received on the falling edge).

		fsl,fsync-rising-edge:
		$ref: /schemas/types.yaml#/definitions/flag
		description:
		Frame sync pulses are sampled with the rising edge of the channel
		clock. If 'fsync-rising-edge' is not present, pulses are sampled with
		the falling edge.

		fsl,double-speed-clock:
		$ref: /schemas/types.yaml#/definitions/flag
		description:
		The channel clock is twice the data rate.

		patternProperties:
		'^fsl,[rt]x-ts-routes$':
		$ref: /schemas/types.yaml#/definitions/uint32-matrix
		description: \|
		A list of tuple that indicates the Tx or Rx time-slots routes.
		items:
		items:
		- description:
		The number of time-slots
		minimum: 1
		maximum: 64
		- description: \|
		The source (Tx) or destination (Rx) serial interface
		(dt-bindings/soc/cpm1-fsl,tsa.h defines these values)
		- 0: No destination
		- 1: SCC2
		- 2: SCC3
		- 3: SCC4
		- 4: SMC1
		- 5: SMC2
		enum: [0, 1, 2, 3, 4, 5]
		minItems: 1
		maxItems: 64

		allOf:
		# If fsl,common-rxtx-pins is present, only 2 clocks are needed.
		# Else, the 4 clocks must be present.
		- if:
		required:
		- fsl,common-rxtx-pins
		then:
		properties:
		clocks:
		maxItems: 2
		clock-names:
		maxItems: 2
		else:
		properties:
		clocks:
		minItems: 4
		clock-names:
		minItems: 4

		required:
		- reg
		- clocks
		- clock-names

		required:
		- compatible
		- reg
		- reg-names
		- '#address-cells'
		- '#size-cells'

		additionalProperties: false

		examples:
		- \|
		#include <dt-bindings/soc/cpm1-fsl,tsa.h>

		tsa@ae0 {
		compatible = "fsl,mpc885-tsa", "fsl,cpm1-tsa";
		reg = <0xae0 0x10>,
		<0xc00 0x200>;
		reg-names = "si_regs", "si_ram";

		#address-cells = <1>;
		#size-cells = <0>;

		tdm@0 {
		/* TDMa */
		reg = <0>;

		clocks = <&clk_l1rsynca>, <&clk_l1rclka>;
		clock-names = "l1rsync", "l1rclk";

		fsl,common-rxtx-pins;
		fsl,fsync-rising-edge;

		fsl,tx-ts-routes = <2 0>, /* TS 0..1 */
		<24 FSL_CPM_TSA_SCC4>, /* TS 2..25 */
		<1 0>, /* TS 26 */
		<5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */

		fsl,rx-ts-routes = <2 0>, /* TS 0..1 */
		<24 FSL_CPM_TSA_SCC4>, /* 2..25 */
		<1 0>, /* TS 26 */
		<5 FSL_CPM_TSA_SCC3>; /* TS 27..31 */
		};
		};