Commit fb0b8d1a authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Convert ID_PFR0_EL1 to automatic generation 



Convert ID_PFR0_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20221130171637.718182-30-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent 5ea58a1b

arch/arm64/include/asm/sysreg.h

+0 −8
Original line number Diff line number Diff line
@@ -165,7 +165,6 @@ 
#define SYS_MPIDR_EL1			sys_reg(3, 0, 0, 0, 5)

#define SYS_REVIDR_EL1			sys_reg(3, 0, 0, 0, 6)



#define SYS_ID_PFR0_EL1			sys_reg(3, 0, 0, 1, 0)

#define SYS_ID_PFR1_EL1			sys_reg(3, 0, 0, 1, 1)

#define SYS_ID_PFR2_EL1			sys_reg(3, 0, 0, 3, 4)

#define SYS_ID_DFR0_EL1			sys_reg(3, 0, 0, 1, 2)
@@ -688,13 +687,6 @@ 


#define ID_MMFR5_EL1_ETS_SHIFT		0



#define ID_PFR0_EL1_DIT_SHIFT		24

#define ID_PFR0_EL1_CSV2_SHIFT		16

#define ID_PFR0_EL1_State3_SHIFT	12

#define ID_PFR0_EL1_State2_SHIFT	8

#define ID_PFR0_EL1_State1_SHIFT	4

#define ID_PFR0_EL1_State0_SHIFT	0



#define ID_DFR0_EL1_PerfMon_SHIFT	24

#define ID_DFR0_EL1_MProfDbg_SHIFT	20

#define ID_DFR0_EL1_MMapTrc_SHIFT	16

arch/arm64/tools/sysreg

+41 −0
Original line number Diff line number Diff line
@@ -46,6 +46,47 @@ 
# feature that introduces them (eg, FEAT_LS64_ACCDATA introduces enumeration

# item ACCDATA) though it may be more taseful to do something else.



Sysreg ID_PFR0_EL1	3	0	0	1	0

Res0	63:32

Enum	31:28	RAS

	0b0000	NI

	0b0001	RAS

	0b0010	RASv1p1

EndEnum

Enum	27:24	DIT

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	23:20	AMU

	0b0000	NI

	0b0001	AMUv1

	0b0010	AMUv1p1

EndEnum

Enum	19:16	CSV2

	0b0000	UNDISCLOSED

	0b0001	IMP

	0b0010	CSV2p1

EndEnum

Enum	15:12	State3

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	11:8	State2

	0b0000	NI

	0b0001	NO_CV

	0b0010	CV

EndEnum

Enum	7:4	State1

	0b0000	NI

	0b0001	THUMB

	0b0010	THUMB2

EndEnum

Enum	3:0	State0

	0b0000	NI

	0b0001	IMP

EndEnum

EndSysreg



Sysreg ID_MMFR0_EL1	3	0	0	1	4

Res0	63:32

Enum	31:28	InnerShr