Commit 5ea58a1b authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Convert ID_ISAR6_EL1 to automatic generation 



Convert ID_ISAR6_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-29-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent f4e9ce12

arch/arm64/include/asm/sysreg.h

+0 −10
Original line number Diff line number Diff line
@@ -173,8 +173,6 @@ 
#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)

#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)



#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)



#define SYS_MVFR0_EL1			sys_reg(3, 0, 0, 3, 0)

#define SYS_MVFR1_EL1			sys_reg(3, 0, 0, 3, 1)

#define SYS_MVFR2_EL1			sys_reg(3, 0, 0, 3, 2)
@@ -688,14 +686,6 @@ 


#define ID_DFR1_EL1_MTPMU_SHIFT		0



#define ID_ISAR6_EL1_I8MM_SHIFT		24

#define ID_ISAR6_EL1_BF16_SHIFT		20

#define ID_ISAR6_EL1_SPECRES_SHIFT	16

#define ID_ISAR6_EL1_SB_SHIFT		12

#define ID_ISAR6_EL1_FHM_SHIFT		8

#define ID_ISAR6_EL1_DP_SHIFT		4

#define ID_ISAR6_EL1_JSCVT_SHIFT	0



#define ID_MMFR5_EL1_ETS_SHIFT		0



#define ID_PFR0_EL1_DIT_SHIFT		24

arch/arm64/tools/sysreg

+32 −0
Original line number Diff line number Diff line
@@ -455,6 +455,38 @@ Enum 3:0 SEVL 
EndEnum

EndSysreg



Sysreg ID_ISAR6_EL1	3	0	0	2	7

Res0	63:28

Enum	27:24	I8MM

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	23:20	BF16

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	19:16	SPECRES

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	15:12	SB

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	11:8	FHM

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	7:4	DP

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	3:0	JSCVT

	0b0000	NI

	0b0001	IMP

EndEnum

EndSysreg



Sysreg ID_MMFR4_EL1	3	0	0	2	6

Res0	63:32

Enum	31:28	EVT