Commit fab9516f authored by Adam Guerin's avatar Adam Guerin Committed by Herbert Xu
Browse files

crypto: qat - fix crypto capability detection for 4xxx 



When extending the capability detection logic for 4xxx devices the
SMx algorithms were accidentally missed.
Enable these SMx capabilities by default for QAT GEN4 devices.

Check for device variants where the SMx algorithms are explicitly
disabled by the GEN4 hardware. This is indicated in fusectl1
register.
Mask out SM3 and SM4 based on a bit specific to those algorithms.
Mask out SM2 if the PKE slice is not present.

Fixes: 4b44d28c ("crypto: qat - extend crypto capability detection for 4xxx")
Signed-off-by: default avatarAdam Guerin <adam.guerin@intel.com>
Reviewed-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent b0cc7491

drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c

+9 −0
Original line number Diff line number Diff line
@@ -225,6 +225,8 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev) 
			  ICP_ACCEL_CAPABILITIES_HKDF |

			  ICP_ACCEL_CAPABILITIES_CHACHA_POLY |

			  ICP_ACCEL_CAPABILITIES_AESGCM_SPC |

			  ICP_ACCEL_CAPABILITIES_SM3 |

			  ICP_ACCEL_CAPABILITIES_SM4 |

			  ICP_ACCEL_CAPABILITIES_AES_V2;



	/* A set bit in fusectl1 means the feature is OFF in this SKU */
@@ -248,12 +250,19 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev) 
		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}



	if (fusectl1 & ICP_ACCEL_4XXX_MASK_SMX_SLICE) {

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM3;

		capabilities_sym &= ~ICP_ACCEL_CAPABILITIES_SM4;

	}



	capabilities_asym = ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |

			  ICP_ACCEL_CAPABILITIES_CIPHER |

			  ICP_ACCEL_CAPABILITIES_SM2 |

			  ICP_ACCEL_CAPABILITIES_ECEDMONT;



	if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {

		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;

		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_SM2;

		capabilities_asym &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;

	}

drivers/crypto/intel/qat/qat_common/icp_qat_hw.h

+4 −1
Original line number Diff line number Diff line
@@ -97,7 +97,10 @@ enum icp_qat_capabilities_mask { 
	ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15),

	ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16),

	ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17),

	/* Bits 18-21 are currently reserved */

	ICP_ACCEL_CAPABILITIES_SM2 = BIT(18),

	ICP_ACCEL_CAPABILITIES_SM3 = BIT(19),

	ICP_ACCEL_CAPABILITIES_SM4 = BIT(20),

	/* Bit 21 is currently reserved */

	ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY = BIT(22),

	ICP_ACCEL_CAPABILITIES_CNV_INTEGRITY64 = BIT(23),

	ICP_ACCEL_CAPABILITIES_LZ4_COMPRESSION = BIT(24),