Commit 4b44d28c authored by Giovanni Cabiddu's avatar Giovanni Cabiddu Committed by Herbert Xu
Browse files

crypto: qat - extend crypto capability detection for 4xxx 



Extended the capability detection logic for 4xxx devices.
Mask out unsupported algorithms and services based on the value read in
the fuse register.

This includes only capabilities for the crypto service.

Signed-off-by: default avatarGiovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: default avatarMarco Chiappero <marco.chiappero@intel.com>
Reviewed-by: default avatarFiona Trahe <fiona.trahe@intel.com>
Reviewed-by: default avatarMarco Chiappero <marco.chiappero@intel.com>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent cfe4894e

drivers/crypto/qat/qat_4xxx/adf_4xxx_hw_data.c

+26 −3
Original line number Diff line number Diff line
@@ -98,18 +98,41 @@ static u32 get_accel_cap(struct adf_accel_dev *accel_dev) 
	u32 fusectl1;

	u32 capabilities = ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC |

			   ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC |

			   ICP_ACCEL_CAPABILITIES_CIPHER |

			   ICP_ACCEL_CAPABILITIES_AUTHENTICATION |

			   ICP_ACCEL_CAPABILITIES_SHA3 |

			   ICP_ACCEL_CAPABILITIES_SHA3_EXT |

			   ICP_ACCEL_CAPABILITIES_HKDF |

			   ICP_ACCEL_CAPABILITIES_ECEDMONT |

			   ICP_ACCEL_CAPABILITIES_CHACHA_POLY |

			   ICP_ACCEL_CAPABILITIES_AESGCM_SPC |

			   ICP_ACCEL_CAPABILITIES_AES_V2;



	/* Read accelerator capabilities mask */

	pci_read_config_dword(pdev, ADF_4XXX_FUSECTL1_OFFSET, &fusectl1);



	if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE)

	/* A set bit in fusectl1 means the feature is OFF in this SKU */

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_CIPHER_SLICE) {

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC;

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE)

		capabilities &= ~ICP_ACCEL_CAPABILITIES_HKDF;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_UCS_SLICE) {

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CHACHA_POLY;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_AESGCM_SPC;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_AES_V2;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_AUTH_SLICE) {

		capabilities &= ~ICP_ACCEL_CAPABILITIES_AUTHENTICATION;

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE)

		capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_SHA3_EXT;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CIPHER;

	}

	if (fusectl1 & ICP_ACCEL_4XXX_MASK_PKE_SLICE) {

		capabilities &= ~ICP_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC;

		capabilities &= ~ICP_ACCEL_CAPABILITIES_ECEDMONT;

	}



	return capabilities;

}

drivers/crypto/qat/qat_common/icp_qat_hw.h

+8 −1
Original line number Diff line number Diff line
@@ -91,7 +91,14 @@ enum icp_qat_capabilities_mask { 
	ICP_ACCEL_CAPABILITIES_RAND = BIT(7),

	ICP_ACCEL_CAPABILITIES_ZUC = BIT(8),

	ICP_ACCEL_CAPABILITIES_SHA3 = BIT(9),

	/* Bits 10-25 are currently reserved */

	/* Bits 10-11 are currently reserved */

	ICP_ACCEL_CAPABILITIES_HKDF = BIT(12),

	ICP_ACCEL_CAPABILITIES_ECEDMONT = BIT(13),

	/* Bit 14 is currently reserved */

	ICP_ACCEL_CAPABILITIES_SHA3_EXT = BIT(15),

	ICP_ACCEL_CAPABILITIES_AESGCM_SPC = BIT(16),

	ICP_ACCEL_CAPABILITIES_CHACHA_POLY = BIT(17),

	/* Bits 18-25 are currently reserved */

	ICP_ACCEL_CAPABILITIES_AES_V2 = BIT(26)

};