Commit f9feb882 authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy
Browse files

drm/i915: Start using REG_BIT* macros with CDCLK registers 

Lets start to use REG_BIT* macros, when working with CDCLK
registers, such as CDCLK_CTL, instead of (x << 0) like expressions.

Link: https://patchwork.freedesktop.org/patch/msgid/20220901113011.12080-1-stanislav.lisovskiy@intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
parent 483e3d87

drivers/gpu/drm/i915/i915_reg.h

+10 −10
Original line number Diff line number Diff line
@@ -7077,16 +7077,16 @@ enum skl_power_gate { 


/* CDCLK_CTL */

#define CDCLK_CTL			_MMIO(0x46000)

#define  CDCLK_FREQ_SEL_MASK		(3 << 26)

#define  CDCLK_FREQ_450_432		(0 << 26)

#define  CDCLK_FREQ_540			(1 << 26)

#define  CDCLK_FREQ_337_308		(2 << 26)

#define  CDCLK_FREQ_675_617		(3 << 26)

#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	(3 << 22)

#define  BXT_CDCLK_CD2X_DIV_SEL_1	(0 << 22)

#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	(1 << 22)

#define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)

#define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)

#define  CDCLK_FREQ_SEL_MASK		REG_GENMASK(27, 26)

#define  CDCLK_FREQ_450_432		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 0)

#define  CDCLK_FREQ_540		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)

#define  CDCLK_FREQ_337_308		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)

#define  CDCLK_FREQ_675_617		REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)

#define  BXT_CDCLK_CD2X_DIV_SEL_MASK	REG_GENMASK(23, 22)

#define  BXT_CDCLK_CD2X_DIV_SEL_1	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)

#define  BXT_CDCLK_CD2X_DIV_SEL_1_5	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)

#define  BXT_CDCLK_CD2X_DIV_SEL_2	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 2)

#define  BXT_CDCLK_CD2X_DIV_SEL_4	REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 3)

#define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)

#define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)

#define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)