Commit f9fca892 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-xilinx', 'clk-kunit', 'clk-cs2000' and 'clk-renesas' into clk-next 

 - Kunit tests for clk-gate implementation
 - Convert Cirrus Logic CS2000P driver to regmap, yamlify DT binding and add
   support for dynamic mode

* clk-xilinx:
  clk: zynqmp: replace warn_once with pr_debug for failed clock ops

* clk-kunit:
  clk: gate: Add some kunit test suites

* clk-cs2000:
  clk: cs2000-cp: convert driver to regmap
  clk: cs2000-cp: freeze config during register fiddling
  clk: cs2000-cp: make clock skip setting configurable
  clk: cs2000-cp: add support for dynamic mode
  clk: cs2000-cp: Make aux output function controllable
  dt-bindings: clock: cs2000-cp: document cirrus,dynamic-mode
  dt-bindings: clock: cs2000-cp: document cirrus,clock-skip flag
  dt-bindings: clock: cs2000-cp: document aux-output-source
  dt-bindings: clock: convert cs2000-cp bindings to yaml

* clk-renesas:
  dt-bindings: clock: renesas: Make example 'clocks' parsable
  clk: rs9: Add Renesas 9-series PCIe clock generator driver
  clk: fixed-factor: Introduce devm_clk_hw_register_fixed_factor_index()
  dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator
  clk: renesas: r8a779f0: Add PFC clock
  clk: renesas: r8a779f0: Add I2C clocks
  clk: renesas: r8a779f0: Add WDT clock
  clk: renesas: r8a779f0: Fix RSW2 clock divider
  clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC
  dt-bindings: clock: renesas: Document RZ/V2L SoC
  dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
  clk: renesas: r8a779a0: Add CANFD module clock
  clk: renesas: r9a07g044: Update multiplier and divider values for PLL2/3
  clk: renesas: r8a7799[05]: Add MLP clocks
  clk: renesas: r8a779f0: Add SYS-DMAC clocks
parents 407c04d6 4917394e a992acbb 5edffb98 3b1db05c

Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier



maintainers:

  - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>



description: |

  The CS2000-CP is an extremely versatile system clocking device that

  utilizes a programmable phase lock loop.



  Link: https://www.cirrus.com/products/cs2000/



properties:

  compatible:

    enum:

      - cirrus,cs2000-cp



  clocks:

    description:

      Common clock binding for CLK_IN, XTI/REF_CLK

    minItems: 2

    maxItems: 2



  clock-names:

    items:

      - const: clk_in

      - const: ref_clk



  '#clock-cells':

    const: 0



  reg:

    maxItems: 1



  cirrus,aux-output-source:

    description:

      Specifies the function of the auxiliary clock output pin

    $ref: /schemas/types.yaml#/definitions/uint32

    enum:

      - 0 # CS2000CP_AUX_OUTPUT_REF_CLK:  ref_clk input

      - 1 # CS2000CP_AUX_OUTPUT_CLK_IN:   clk_in input

      - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT:  clk_out output

      - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status

    default: 0



  cirrus,clock-skip:

    description:

      This mode allows the PLL to maintain lock even when CLK_IN

      has missing pulses for up to 20 ms.

    $ref: /schemas/types.yaml#/definitions/flag



  cirrus,dynamic-mode:

    description:

      In dynamic mode, the CLK_IN input is used to drive the

      digital PLL of the silicon.

      If not given, the static mode shall be used to derive the

      output signal directly from the REF_CLK input.

    $ref: /schemas/types.yaml#/definitions/flag



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/cirrus,cs2000-cp.h>



    i2c@0 {

      reg = <0x0 0x100>;

      #address-cells = <1>;

      #size-cells = <0>;



      clock-controller@4f {

        #clock-cells = <0>;

        compatible = "cirrus,cs2000-cp";

        reg = <0x4f>;

        clocks = <&rcar_sound 0>, <&x12_clk>;

        clock-names = "clk_in", "ref_clk";

        cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;

      };

    };

Documentation/devicetree/bindings/clock/cs2000-cp.txt

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CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier



Required properties:



- compatible:		"cirrus,cs2000-cp"

- reg:			The chip select number on the I2C bus

- clocks:		common clock binding for CLK_IN, XTI/REF_CLK

- clock-names:		CLK_IN : clk_in, XTI/REF_CLK : ref_clk

- #clock-cells:		must be <0>



Example:



&i2c2 {

	...

	cs2000: clk_multiplier@4f {

		#clock-cells = <0>;

		compatible = "cirrus,cs2000-cp";

		reg = <0x4f>;

		clocks = <&rcar_sound 0>, <&x12_clk>;

		clock-names = "clk_in", "ref_clk";

	};

};

Documentation/devicetree/bindings/clock/renesas,9series.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/renesas,9series.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Binding for Renesas 9-series I2C PCIe clock generators



description: |

  The Renesas 9-series are I2C PCIe clock generators providing

  from 1 to 20 output clocks.



  When referencing the provided clock in the DT using phandle

  and clock specifier, the following mapping applies:



  - 9FGV0241:

    0 -- DIF0

    1 -- DIF1



maintainers:

  - Marek Vasut <marex@denx.de>



properties:

  compatible:

    enum:

      - renesas,9fgv0241



  reg:

    description: I2C device address

    enum: [ 0x68, 0x6a ]



  '#clock-cells':

    const: 1



  clocks:

    items:

      - description: XTal input clock



  renesas,out-amplitude-microvolt:

    enum: [ 600000, 700000, 800000, 900000 ]

    description: Output clock signal amplitude



  renesas,out-spread-spectrum:

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 100000, 99750, 99500 ]

    description: Output clock down spread in pcm (1/1000 of percent)



patternProperties:

  "^DIF[0-19]$":

    type: object

    description:

      Description of one of the outputs (DIF0..DIF19).



    properties:

      renesas,slew-rate:

        $ref: /schemas/types.yaml#/definitions/uint32

        enum: [ 2000000, 3000000 ]

        description: Output clock slew rate select in V/ns



    additionalProperties: false



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  - |

    /* 25MHz reference crystal */

    ref25: ref25m {

        compatible = "fixed-clock";

        #clock-cells = <0>;

        clock-frequency = <25000000>;

    };



    i2c@0 {

        reg = <0x0 0x100>;

        #address-cells = <1>;

        #size-cells = <0>;



        rs9: clock-generator@6a {

            compatible = "renesas,9fgv0241";

            reg = <0x6a>;

            #clock-cells = <1>;



            clocks = <&ref25m>;



            DIF0 {

                renesas,slew-rate = <3000000>;

            };

        };

    };



...

Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml

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@@ -51,6 +51,18 @@ additionalProperties: false 
examples:

  - |

    #include <dt-bindings/clock/r8a73a4-clock.h>



    cpg_clocks: cpg_clocks@e6150000 {

            compatible = "renesas,r8a73a4-cpg-clocks";

            reg = <0xe6150000 0x10000>;

            clocks = <&extal1_clk>, <&extal2_clk>;

            #clock-cells = <1>;

            clock-output-names = "main", "pll0", "pll1", "pll2",

                                  "pll2s", "pll2h", "z", "z2",

                                  "i", "m3", "b", "m1", "m2",

                                  "zx", "zs", "hp";

    };



    sdhi2_clk: sdhi2_clk@e615007c {

            compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";

            reg = <0xe615007c 4>;

Documentation/devicetree/bindings/clock/renesas,rzg2l-cpg.yaml

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@@ -4,13 +4,13 @@ 
$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"

$schema: "http://devicetree.org/meta-schemas/core.yaml#"



title: Renesas RZ/G2L Clock Pulse Generator / Module Standby Mode

title: Renesas RZ/{G2L,V2L} Clock Pulse Generator / Module Standby Mode



maintainers:

  - Geert Uytterhoeven <geert+renesas@glider.be>



description: |

  On Renesas RZ/G2L SoC, the CPG (Clock Pulse Generator) and Module

  On Renesas RZ/{G2L,V2L} SoC, the CPG (Clock Pulse Generator) and Module

  Standby Mode share the same register block.



  They provide the following functionalities:
@@ -22,7 +22,9 @@ description: | 


properties:

  compatible:

    const: renesas,r9a07g044-cpg  # RZ/G2{L,LC}

    enum:

      - renesas,r9a07g044-cpg  # RZ/G2{L,LC}

      - renesas,r9a07g054-cpg  # RZ/V2L



  reg:

    maxItems: 1
@@ -40,9 +42,9 @@ properties: 
    description: |

      - For CPG core clocks, the two clock specifier cells must be "CPG_CORE"

        and a core clock reference, as defined in

        <dt-bindings/clock/r9a07g044-cpg.h>

        <dt-bindings/clock/r9a07g*-cpg.h>

      - For module clocks, the two clock specifier cells must be "CPG_MOD" and

        a module number, as defined in the <dt-bindings/clock/r9a07g044-cpg.h>.

        a module number, as defined in the <dt-bindings/clock/r9a07g0*-cpg.h>.

    const: 2



  '#power-domain-cells':
@@ -56,7 +58,7 @@ properties: 
  '#reset-cells':

    description:

      The single reset specifier cell must be the module number, as defined in

      the <dt-bindings/clock/r9a07g044-cpg.h>.

      the <dt-bindings/clock/r9a07g0*-cpg.h>.

    const: 1



required: