Commit 407c04d6 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge branches 'clk-microchip', 'clk-si', 'clk-mtk', 'clk-at91' and 'clk-st' into clk-next 

 - Clock configuration on Microchip PolarFire SoCs
 - Free allocations on probe error in Mediatek clk driver
 - Modernize Mediatek clk driver by consolidating code

* clk-microchip:
  clk: microchip: Add driver for Microchip PolarFire SoC
  dt-bindings: clk: microchip: Add Microchip PolarFire host binding

* clk-si:
  clk-si5341: replace snprintf in show functions with sysfs_emit
  clk: si5341: fix reported clk_rate when output divider is 2

* clk-mtk: (32 commits)
  clk: mediatek: Warn if clk IDs are duplicated
  clk: mediatek: mt8195: Implement remove functions
  clk: mediatek: mt8195: Implement error handling in probe functions
  clk: mediatek: mt8195: Hook up mtk_clk_simple_remove()
  clk: mediatek: Unregister clks in mtk_clk_simple_probe() error path
  clk: mediatek: mtk: Implement error handling in register APIs
  clk: mediatek: pll: Implement error handling in register API
  clk: mediatek: mux: Implement error handling in register API
  clk: mediatek: mux: Reverse check for existing clk to reduce nesting level
  clk: mediatek: gate: Implement error handling in register API
  clk: mediatek: cpumux: Implement error handling in register API
  clk: mediatek: mtk: Clean up included headers
  clk: mediatek: Add mtk_clk_simple_remove()
  clk: mediatek: Implement mtk_clk_unregister_composites() API
  clk: mediatek: Implement mtk_clk_unregister_divider_clks() API
  clk: mediatek: Implement mtk_clk_unregister_factors() API
  clk: mediatek: Implement mtk_clk_unregister_fixed_clks() API
  clk: mediatek: pll: Clean up included headers
  clk: mediatek: pll: Implement unregister API
  clk: mediatek: pll: Split definitions into separate header file
  ...

* clk-at91:
  clk: at91: clk-master: remove dead code
  clk: at91: sama7g5: fix parents of PDMCs' GCLK
  clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DT
  clk: at91: allow setting PMC_AUDIOPINCK clock parents via DT

* clk-st:
  clk: stm32mp1: Add parent_data to ETHRX clock
  clk: stm32mp1: Split ETHCK_K into separate MUX and GATE clock
parents 754e0b0e 635e5e73 982c5953 d54bb86b 34f74978 e9ed1ef1

Documentation/devicetree/bindings/clock/microchip,mpfs.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Microchip PolarFire Clock Control Module Binding



maintainers:

  - Daire McNamara <daire.mcnamara@microchip.com>



description: |

  Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,

  which gates and enables all peripheral clocks.



  This device tree binding describes 33 gate clocks.  Clocks are referenced by

  user nodes by the CLKCFG node phandle and the clock index in the group, from

  0 to 32.



properties:

  compatible:

    const: microchip,mpfs-clkcfg



  reg:

    maxItems: 1



  clocks:

    maxItems: 1



  '#clock-cells':

    const: 1

    description: |

      The clock consumer should specify the desired clock by having the clock

      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h

      for the full list of PolarFire clock IDs.



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'



additionalProperties: false



examples:

  # Clock Config node:

  - |

    #include <dt-bindings/clock/microchip,mpfs-clock.h>

    soc {

            #address-cells = <2>;

            #size-cells = <2>;

            clkcfg: clock-controller@20002000 {

                compatible = "microchip,mpfs-clkcfg";

                reg = <0x0 0x20002000 0x0 0x1000>;

                clocks = <&ref>;

                #clock-cells = <1>;

        };

    };

drivers/clk/Kconfig

+1 −3
Original line number Diff line number Diff line
@@ -330,9 +330,6 @@ config COMMON_CLK_PXA 
	help

	  Support for the Marvell PXA SoC.



config COMMON_CLK_PIC32

	def_bool COMMON_CLK && MACH_PIC32



config COMMON_CLK_OXNAS

	bool "Clock driver for the OXNAS SoC Family"

	depends on ARCH_OXNAS || COMPILE_TEST
@@ -407,6 +404,7 @@ source "drivers/clk/keystone/Kconfig" 
source "drivers/clk/mediatek/Kconfig"

source "drivers/clk/meson/Kconfig"

source "drivers/clk/mstar/Kconfig"

source "drivers/clk/microchip/Kconfig"

source "drivers/clk/mvebu/Kconfig"

source "drivers/clk/pistachio/Kconfig"

source "drivers/clk/qcom/Kconfig"

drivers/clk/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -91,7 +91,7 @@ obj-$(CONFIG_ARCH_KEYSTONE) += keystone/ 
obj-$(CONFIG_MACH_LOONGSON32)		+= loongson1/

obj-y					+= mediatek/

obj-$(CONFIG_ARCH_MESON)		+= meson/

obj-$(CONFIG_MACH_PIC32)		+= microchip/

obj-y					+= microchip/

ifeq ($(CONFIG_COMMON_CLK), y)

obj-$(CONFIG_ARCH_MMP)			+= mmp/

endif

drivers/clk/at91/at91rm9200.c

+1 −2
Original line number Diff line number Diff line
@@ -143,8 +143,7 @@ static void __init at91rm9200_pmc_setup(struct device_node *np) 
					   parent_names,

					   &at91rm9200_master_layout,

					   &rm9200_mck_characteristics,

					   &rm9200_mck_lock, CLK_SET_RATE_GATE,

					   INT_MIN);

					   &rm9200_mck_lock);

	if (IS_ERR(hw))

		goto err_free;

drivers/clk/at91/at91sam9260.c

+1 −2
Original line number Diff line number Diff line
@@ -419,8 +419,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np, 
					   parent_names,

					   &at91rm9200_master_layout,

					   data->mck_characteristics,

					   &at91sam9260_mck_lock,

					   CLK_SET_RATE_GATE, INT_MIN);

					   &at91sam9260_mck_lock);

	if (IS_ERR(hw))

		goto err_free;