Unverified Commit f962dafb authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!3634 Intel: Backport Granite Rapids(GNR) core PMU support to OLK-5.10 

Merge Pull Request from: @yunyingsun 
 
Title: Add core PMU support for Intel Granite Rapids

Content:
This PR adds core Performance Monitoring Unit(PMU) support for next Intel Xeon platform Granite Rapids(GNR).

It contains 3 enabling commits and 1 following bugfix commit from mainline kernel.

v6.4-rc1(3 commits):
872d2800 perf/x86/cstate: Add Granite Rapids support
5a796d5c perf/x86/msr: Add Granite Rapids
bc4000fd perf/x86/intel: Add Granite Rapids

Following fix from v6.4(1 commit):
a6742cb9 perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL

The backported patches are identical with the mainline commits.

Intel-kernel issue:
https://gitee.com/openeuler/intel-kernel/issues/I8RV41

Test:
Platform dependent core PMU events work with perf, like "L1-dcache-loads".
With this PR applied to kernel OLK-5.10, all core PMU events work on GNR.

Known issue:
N/A

Default config change:
N/A 
 
Link:https://gitee.com/openeuler/kernel/pulls/3634

 

Reviewed-by: default avatarJason Zeng <jason.zeng@intel.com>
Reviewed-by: default avatarAichun Shi <aichun.shi@intel.com>
Reviewed-by: default avatarXu Kuohai <xukuohai@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents dcb61069 bef0f5da

arch/x86/events/intel/core.c

+27 −3
Original line number Diff line number Diff line
@@ -326,6 +326,16 @@ static struct event_constraint intel_spr_event_constraints[] = { 
	EVENT_CONSTRAINT_END

};



static struct extra_reg intel_gnr_extra_regs[] __read_mostly = {

	INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),

	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),

	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),

	INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),

	INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),

	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),

	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),

	EVENT_EXTRA_END

};



EVENT_ATTR_STR(mem-loads,	mem_ld_nhm,	"event=0x0b,umask=0x10,ldlat=3");

EVENT_ATTR_STR(mem-loads,	mem_ld_snb,	"event=0xcd,umask=0x1,ldlat=3");
@@ -5464,6 +5474,15 @@ pebs_is_visible(struct kobject *kobj, struct attribute *attr, int i) 
	return x86_pmu.pebs ? attr->mode : 0;

}



static umode_t

mem_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{

	if (attr == &event_attr_mem_ld_aux.attr.attr)

		return x86_pmu.flags & PMU_FL_MEM_LOADS_AUX ? attr->mode : 0;



	return pebs_is_visible(kobj, attr, i);

}



static umode_t

lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i)

{
@@ -5491,7 +5510,7 @@ static struct attribute_group group_events_td = { 


static struct attribute_group group_events_mem = {

	.name       = "events",

	.is_visible = pebs_is_visible,

	.is_visible = mem_is_visible,

};



static struct attribute_group group_events_tsx = {
@@ -6500,6 +6519,11 @@ __init int intel_pmu_init(void) 


	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		fallthrough;

	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:

		pmem = true;

		x86_pmu.late_ack = true;

		memcpy(hw_cache_event_ids, spr_hw_cache_event_ids, sizeof(hw_cache_event_ids));
@@ -6507,7 +6531,8 @@ __init int intel_pmu_init(void) 


		x86_pmu.event_constraints = intel_spr_event_constraints;

		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		if (!x86_pmu.extra_regs)

			x86_pmu.extra_regs = intel_gnr_extra_regs;

		x86_pmu.limit_period = spr_limit_period;

		x86_pmu.pebs_aliases = NULL;

		x86_pmu.pebs_prec_dist = true;
@@ -6516,7 +6541,6 @@ __init int intel_pmu_init(void) 
		x86_pmu.flags |= PMU_FL_NO_HT_SHARING;

		x86_pmu.flags |= PMU_FL_PEBS_ALL;

		x86_pmu.flags |= PMU_FL_INSTR_LATENCY;

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;



		x86_pmu.hw_config = hsw_hw_config;

		x86_pmu.get_event_constraints = spr_get_event_constraints;

arch/x86/events/intel/cstate.c

+2 −0
Original line number Diff line number Diff line
@@ -679,6 +679,8 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = { 
	X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D,		&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X,	&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(EMERALDRAPIDS_X,	&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_X,	&icx_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(GRANITERAPIDS_D,	&icx_cstates),



	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE_L,		&icl_cstates),

	X86_MATCH_INTEL_FAM6_MODEL(TIGERLAKE,		&icl_cstates),

arch/x86/events/msr.c

+2 −0
Original line number Diff line number Diff line
@@ -70,6 +70,8 @@ static bool test_intel(int idx, void *data) 
	case INTEL_FAM6_BROADWELL_X:

	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:



	case INTEL_FAM6_ATOM_SILVERMONT:

	case INTEL_FAM6_ATOM_SILVERMONT_D: