Commit bef0f5da authored by Kan Liang's avatar Kan Liang Committed by Yunying Sun
Browse files

perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL 

mainline inclusion
from mainline-v6.4
commit a6742cb9
category: feature
feature: GNR core PMU
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I8RV41
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=a6742cb90b567f952a95efa27dee345748d09fc7



Intel-SIG: commit a6742cb9 perf/x86/intel: Fix the FRONTEND encoding on GNR and MTL
Backport a following upstream bugfix for GNR core PMU support.

-------------------------------------

When counting a FRONTEND event, the MSR_PEBS_FRONTEND is not correctly
set on GNR and MTL p-core.

The umask value for the FRONTEND events is changed on GNR and MTL. The
new umask is missing in the extra_regs[] table.

Add a dedicated intel_gnr_extra_regs[] for GNR and MTL p-core.

Fixes: bc4000fd ("perf/x86/intel: Add Granite Rapids")
Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20230615173242.3726364-1-kan.liang@linux.intel.com


Signed-off-by: default avatarYunying Sun <yunying.sun@intel.com>
parent 0889138f

arch/x86/events/intel/core.c

+13 −1
Original line number Diff line number Diff line
@@ -326,6 +326,16 @@ static struct event_constraint intel_spr_event_constraints[] = { 
	EVENT_CONSTRAINT_END

};



static struct extra_reg intel_gnr_extra_regs[] __read_mostly = {

	INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),

	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),

	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),

	INTEL_UEVENT_EXTRA_REG(0x02c6, MSR_PEBS_FRONTEND, 0x9, FE),

	INTEL_UEVENT_EXTRA_REG(0x03c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),

	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),

	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),

	EVENT_EXTRA_END

};



EVENT_ATTR_STR(mem-loads,	mem_ld_nhm,	"event=0x0b,umask=0x10,ldlat=3");

EVENT_ATTR_STR(mem-loads,	mem_ld_snb,	"event=0xcd,umask=0x1,ldlat=3");
@@ -5802,6 +5812,7 @@ __init int intel_pmu_init(void) 
	case INTEL_FAM6_SAPPHIRERAPIDS_X:

	case INTEL_FAM6_EMERALDRAPIDS_X:

		x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		fallthrough;

	case INTEL_FAM6_GRANITERAPIDS_X:

	case INTEL_FAM6_GRANITERAPIDS_D:
@@ -5812,7 +5823,8 @@ __init int intel_pmu_init(void) 


		x86_pmu.event_constraints = intel_spr_event_constraints;

		x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints;

		x86_pmu.extra_regs = intel_spr_extra_regs;

		if (!x86_pmu.extra_regs)

			x86_pmu.extra_regs = intel_gnr_extra_regs;

		x86_pmu.limit_period = spr_limit_period;

		x86_pmu.pebs_aliases = NULL;

		x86_pmu.pebs_prec_dist = true;