Commit f8673fd5 authored by Ashok Reddy Soma's avatar Ashok Reddy Soma Committed by Michal Simek
Browse files

arm64: zynqmp: Fix usb node drive strength and slew rate 



As per design, all input/rx pins should have fast slew rate and 12mA
drive strength. Rest all pins should be slow slew rate and 4mA drive
strength. Fix usb nodes as per this and remove setting of slow slew rate
for all the usb group pins.

Signed-off-by: default avatarAshok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/379071f44ceb27a0e32d74e13221640922d989d1.1684767562.git.michal.simek@amd.com
parent c720a1f5

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+6 −2
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for KV260 revA Carrier Card

 *

 * (C) Copyright 2020 - 2021, Xilinx, Inc.

 * (C) Copyright 2020 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * SD level shifter:

 * "A" - A01 board un-modified (NXP)
@@ -265,19 +266,22 @@ 
	pinctrl_usb0_default: usb0-default {

		conf {

			groups = "usb0_0_grp";

			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		conf-rx {

			pins = "MIO52", "MIO53", "MIO55";

			bias-high-impedance;

			drive-strength = <12>;

			slew-rate = <SLEW_RATE_FAST>;

		};



		conf-tx {

			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",

			"MIO60", "MIO61", "MIO62", "MIO63";

			bias-disable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};



		mux {

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+6 −2
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for KV260 revA Carrier Card

 *

 * (C) Copyright 2020 - 2021, Xilinx, Inc.

 * (C) Copyright 2020 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -248,19 +249,22 @@ 
	pinctrl_usb0_default: usb0-default {

		conf {

			groups = "usb0_0_grp";

			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		conf-rx {

			pins = "MIO52", "MIO53", "MIO55";

			bias-high-impedance;

			drive-strength = <12>;

			slew-rate = <SLEW_RATE_FAST>;

		};



		conf-tx {

			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",

			"MIO60", "MIO61", "MIO62", "MIO63";

			bias-disable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};



		mux {

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm015-dc1.dts

+6 −2
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP zc1751-xm015-dc1

 *

 * (C) Copyright 2015 - 2021, Xilinx, Inc.

 * (C) Copyright 2015 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -187,19 +188,22 @@ 


		conf {

			groups = "usb0_0_grp";

			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		conf-rx {

			pins = "MIO52", "MIO53", "MIO55";

			bias-high-impedance;

			drive-strength = <12>;

			slew-rate = <SLEW_RATE_FAST>;

		};



		conf-tx {

			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",

			       "MIO60", "MIO61", "MIO62", "MIO63";

			bias-disable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};

	};

arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dts

+6 −2
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP zc1751-xm016-dc2

 *

 * (C) Copyright 2015 - 2021, Xilinx, Inc.

 * (C) Copyright 2015 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -281,19 +282,22 @@ 


		conf {

			groups = "usb1_0_grp";

			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		conf-rx {

			pins = "MIO64", "MIO65", "MIO67";

			bias-high-impedance;

			drive-strength = <12>;

			slew-rate = <SLEW_RATE_FAST>;

		};



		conf-tx {

			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",

			       "MIO72", "MIO73", "MIO74", "MIO75";

			bias-disable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};

	};

arch/arm64/boot/dts/xilinx/zynqmp-zcu100-revC.dts

+10 −3
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU100 revC

 *

 * (C) Copyright 2016 - 2021, Xilinx, Inc.

 * (C) Copyright 2016 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 * Nathalie Chan King Choy
@@ -432,19 +433,22 @@ 


		conf {

			groups = "usb0_0_grp";

			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		conf-rx {

			pins = "MIO52", "MIO53", "MIO55";

			bias-high-impedance;

			drive-strength = <12>;

			slew-rate = <SLEW_RATE_FAST>;

		};



		conf-tx {

			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",

			       "MIO60", "MIO61", "MIO62", "MIO63";

			bias-disable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};

	};
@@ -456,19 +460,22 @@ 


		conf {

			groups = "usb1_0_grp";

			slew-rate = <SLEW_RATE_SLOW>;

			power-source = <IO_STANDARD_LVCMOS18>;

		};



		conf-rx {

			pins = "MIO64", "MIO65", "MIO67";

			bias-high-impedance;

			drive-strength = <12>;

			slew-rate = <SLEW_RATE_FAST>;

		};



		conf-tx {

			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",

			       "MIO72", "MIO73", "MIO74", "MIO75";

			bias-disable;

			drive-strength = <4>;

			slew-rate = <SLEW_RATE_SLOW>;

		};

	};

};