Commit c720a1f5 authored by Michal Simek's avatar Michal Simek
Browse files

arm64: zynqmp: Describe TI phy as ethernet-phy-id 



TI DP83867 is using strapping based on MIO pins. Tristate setup can
influence PHY address. That's why switch description with ethernet-phy-id
compatible string which enable calling reset. PHY itself setups phy address
after power up or reset. Phy reset is done via gpio.

Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/b49904649a363f40dc9c4d3fa275e42129562082.1684767562.git.michal.simek@amd.com
parent 4e4ddd3d

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revA.dts

+15 −8
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU102 RevA

 *

 * (C) Copyright 2015 - 2021, Xilinx, Inc.

 * (C) Copyright 2015 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -200,13 +201,19 @@ 
	phy-mode = "rgmii-id";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gem3_default>;

	mdio: mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		phy0: ethernet-phy@21 {

			#phy-cells = <1>;

			compatible = "ethernet-phy-id2000.a231";

			reg = <21>;

			ti,rx-internal-delay = <0x8>;

			ti,tx-internal-delay = <0xa>;

			ti,fifo-depth = <0x1>;

			ti,dp83867-rxctrl-strap-quirk;

		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */

			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;

		};

	};

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu102-revB.dts

+15 −10
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU102 RevB

 *

 * (C) Copyright 2016 - 2021, Xilinx, Inc.

 * (C) Copyright 2016 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -16,17 +17,21 @@ 


&gem3 {

	phy-handle = <&phyc>;

	mdio: mdio {

		phyc: ethernet-phy@c {

			#phy-cells = <0x1>;

			compatible = "ethernet-phy-id2000.a231";

			reg = <0xc>;

			ti,rx-internal-delay = <0x8>;

			ti,tx-internal-delay = <0xa>;

			ti,fifo-depth = <0x1>;

			ti,dp83867-rxctrl-strap-quirk;

		/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */

			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;

		};

		/* Cleanup from RevA */

		/delete-node/ ethernet-phy@21;

	};

};



/* Fix collision with u61 */

&i2c0 {

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revA.dts

+15 −7
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU104

 *

 * (C) Copyright 2017 - 2021, Xilinx, Inc.

 * (C) Copyright 2017 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -109,12 +110,19 @@ 
	phy-mode = "rgmii-id";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gem3_default>;

	mdio: mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		phy0: ethernet-phy@c {

			#phy-cells = <1>;

			compatible = "ethernet-phy-id2000.a231";

			reg = <0xc>;

			ti,rx-internal-delay = <0x8>;

			ti,tx-internal-delay = <0xa>;

			ti,fifo-depth = <0x1>;

			ti,dp83867-rxctrl-strap-quirk;

			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;

		};

	};

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu104-revC.dts

+15 −7
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU104

 *

 * (C) Copyright 2017 - 2021, Xilinx, Inc.

 * (C) Copyright 2017 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -114,12 +115,19 @@ 
	phy-mode = "rgmii-id";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gem3_default>;

	mdio: mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		phy0: ethernet-phy@c {

			#phy-cells = <1>;

			compatible = "ethernet-phy-id2000.a231";

			reg = <0xc>;

			ti,rx-internal-delay = <0x8>;

			ti,tx-internal-delay = <0xa>;

			ti,fifo-depth = <0x1>;

			ti,dp83867-rxctrl-strap-quirk;

			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;

		};

	};

};

arch/arm64/boot/dts/xilinx/zynqmp-zcu106-revA.dts

+15 −7
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ 
/*

 * dts file for Xilinx ZynqMP ZCU106

 *

 * (C) Copyright 2016 - 2021, Xilinx, Inc.

 * (C) Copyright 2016 - 2022, Xilinx, Inc.

 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.

 *

 * Michal Simek <michal.simek@amd.com>

 */
@@ -212,12 +213,19 @@ 
	phy-mode = "rgmii-id";

	pinctrl-names = "default";

	pinctrl-0 = <&pinctrl_gem3_default>;

	mdio: mdio {

		#address-cells = <1>;

		#size-cells = <0>;

		phy0: ethernet-phy@c {

			#phy-cells = <1>;

			reg = <0xc>;

			compatible = "ethernet-phy-id2000.a231";

			ti,rx-internal-delay = <0x8>;

			ti,tx-internal-delay = <0xa>;

			ti,fifo-depth = <0x1>;

			ti,dp83867-rxctrl-strap-quirk;

			reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>;

		};

	};

};