Commit 4e4ddd3d authored May 30, 2023 by Michal Simek

arm64: zynqmp: Switch to amd.com emails

Update my and DPs email address to match current setup.

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/108cbbbab29e13d386d38a779fd582f10844a030.1685443337.git.michal.simek@amd.com

parent f5c8855d

arch/arm64/boot/dts/xilinx/avnet-ultra96-rev1.dts

+1 −1

Original line number	Diff line number	Diff line
		@@ -4,7 +4,7 @@
		*
		* (C) Copyright 2018, Xilinx, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Michal Simek <michal.simek@amd.com>
		*/

		/dts-v1/;

arch/arm64/boot/dts/xilinx/zynqmp-clk-ccf.dtsi

+1 −1

Original line number	Diff line number	Diff line
		@@ -5,7 +5,7 @@
		* (C) Copyright 2017 - 2022, Xilinx, Inc.
		* (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Michal Simek <michal.simek@amd.com>
		*/

		#include <dt-bindings/clock/xlnx-zynqmp-clk.h>

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso

+1 −1

Original line number	Diff line number	Diff line
		@@ -9,7 +9,7 @@
		* "Y" - A01 board modified with legacy interposer (Nexperia)
		* "Z" - A01 board modified with Diode interposer
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Michal Simek <michal.simek@amd.com>
		*/

		#include <dt-bindings/gpio/gpio.h>

arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revB.dtso

+1 −1

Original line number	Diff line number	Diff line
		@@ -4,7 +4,7 @@
		*
		* (C) Copyright 2020 - 2021, Xilinx, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Michal Simek <michal.simek@amd.com>
		*/

		#include <dt-bindings/gpio/gpio.h>

arch/arm64/boot/dts/xilinx/zynqmp-sm-k26-revA.dts

+1 −1

Original line number	Diff line number	Diff line
		@@ -4,7 +4,7 @@
		*
		* (C) Copyright 2020 - 2021, Xilinx, Inc.
		*
		* Michal Simek <michal.simek@xilinx.com>
		* Michal Simek <michal.simek@amd.com>
		*/

		/dts-v1/;