EDAC/skx_common: Add new ADXL components for 2-level memory

mainline inclusion
from mainline-v5.14-rc1
commit 2f4348e5
category: feature
bugzilla: https://gitee.com/openeuler/intel-kernel/issues/I5HAC1


CVE: NA

Intel-SIG: commit 2f4348e5 EDAC/skx_common: Add new ADXL components for 2-level
 memory.
Backport to add EDAC 2LM support.

--------------------------------

Some Intel servers may configure memory in 2 levels, using
fast "near" memory (e.g. DDR) as a cache for larger, slower,
"far" memory (e.g. 3D X-point).

In these configurations the BIOS ADXL address translation for
an address in a 2-level memory range will provide details of
both the "near" and far components.

Current exported ADXL components are only for 1-level memory
system or for 2nd level memory of 2-level memory system. So
add new ADXL components for 1st level memory of 2-level memory
system to fully support 2-level memory system and the detection
of memory error source(1st level memory or 2nd level memory).

Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Link: https://lore.kernel.org/r/20210611170123.1057025-2-tony.luck@intel.com


Signed-off-by: Youquan Song <youquan.song@intel.com>