Commit f817c132 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Stephen Boyd
Browse files

clk: socfpga: agilex: fix up s2f_user0_clk representation 



Correct the s2f_user0_mux clock representation.

Fixes: 80c6b7a0 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarKris Chaplin <kris.chaplin@intel.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-2-dinguyen@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9d563236

drivers/clk/socfpga/clk-agilex.c

+9 −0
Original line number Diff line number Diff line
@@ -195,6 +195,13 @@ static const struct clk_parent_data sdmmc_mux[] = { 
	  .name = "boot_clk", },

};



static const struct clk_parent_data s2f_user0_mux[] = {

	{ .fw_name = "s2f_user0_free_clk",

	  .name = "s2f_user0_free_clk", },

	{ .fw_name = "boot_clk",

	  .name = "boot_clk", },

};



static const struct clk_parent_data s2f_user1_mux[] = {

	{ .fw_name = "s2f_user1_free_clk",

	  .name = "s2f_user1_free_clk", },
@@ -319,6 +326,8 @@ static const struct stratix10_gate_clock agilex_gate_clks[] = { 
	  4, 0x98, 0, 16, 0x88, 3, 0},

	{ AGILEX_SDMMC_CLK, "sdmmc_clk", NULL, sdmmc_mux, ARRAY_SIZE(sdmmc_mux), 0, 0x7C,

	  5, 0, 0, 0, 0x88, 4, 4},

	{ AGILEX_S2F_USER0_CLK, "s2f_user0_clk", NULL, s2f_user0_mux, ARRAY_SIZE(s2f_user0_mux), 0, 0x24,

	  6, 0, 0, 0, 0x30, 2, 0},

	{ AGILEX_S2F_USER1_CLK, "s2f_user1_clk", NULL, s2f_user1_mux, ARRAY_SIZE(s2f_user1_mux), 0, 0x7C,

	  6, 0, 0, 0, 0x88, 5, 0},

	{ AGILEX_PSI_REF_CLK, "psi_ref_clk", NULL, psi_mux, ARRAY_SIZE(psi_mux), 0, 0x7C,