Commit 9d563236 authored by Dinh Nguyen's avatar Dinh Nguyen Committed by Stephen Boyd
Browse files

clk: socfpga: agilex: fix the parents of the psi_ref_clk 



The psi_ref_clk comes from the C2 node of the main_pll and periph_pll,
not the C3.

Fixes: 80c6b7a0 ("clk: socfpga: agilex: add clock driver for the Agilex platform")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarKris Chaplin <kris.chaplin@intel.com>
Signed-off-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20210713144621.605140-1-dinguyen@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent e73f0f0e

drivers/clk/socfpga/clk-agilex.c

+4 −4
Original line number Diff line number Diff line
@@ -107,10 +107,10 @@ static const struct clk_parent_data gpio_db_free_mux[] = { 
};



static const struct clk_parent_data psi_ref_free_mux[] = {

	{ .fw_name = "main_pll_c3",

	  .name = "main_pll_c3", },

	{ .fw_name = "peri_pll_c3",

	  .name = "peri_pll_c3", },

	{ .fw_name = "main_pll_c2",

	  .name = "main_pll_c2", },

	{ .fw_name = "peri_pll_c2",

	  .name = "peri_pll_c2", },

	{ .fw_name = "osc1",

	  .name = "osc1", },

	{ .fw_name = "cb-intosc-hs-div2-clk",